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| mo t o rol a .com/s e m i c o n d uc t ors m68hc08 microcontrollers MC68HC908JB16 technical data MC68HC908JB16/d rev. 1, 5/2002 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola 3 MC68HC908JB16 technical data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola, inc. is an equal opportunity/affirmative action employer. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. ? motorola, inc., 2002 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . revision history technical data MC68HC908JB16 ? rev. 1.0 4 motorola to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://motorola.com/semiconductors the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) may 2002 1 first general release. ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola list of sections 5 technical data ? MC68HC908JB16 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . . . . 29 section 2. memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 section 3. random-access memory (ram) . . . . . . . . . . . . . 57 section 4. flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 section 5. configuration register (config) . . . . . . . . . . . . 71 section 6. central processor unit (cpu). . . . . . . . . . . . . . . . 75 section 7. oscillator (osc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 section 8. system integration module (sim) . . . . . . . . . . . . . 97 section 9. monitor rom (mon) . . . . . . . . . . . . . . . . . . . . . . 123 section 10. timer interface module (tim) . . . . . . . . . . . . . . 137 section 11. universal serial bus module (usb) . . . . . . . . . 161 section 12. serial communications interface module (sci). . . . . . . . . . . . . . . . . . . . . . . . . . . 207 section 13. clock generator module (cgm) . . . . . . . . . . . . 247 section 14. input/output (i/o) ports. . . . . . . . . . . . . . . . . . . 263 section 15. external interrupt (irq) . . . . . . . . . . . . . . . . . . . 281 section 16. keyboard interrupt module (kbi) . . . . . . . . . . . 289 section 17. computer operating properly (cop) . . . . . . . . 297 section 18. low-voltage inhibit (lvi) . . . . . . . . . . . . . . . . . 303 section 19. break module (brk) . . . . . . . . . . . . . . . . . . . . . 307 section 20. electrical specifications . . . . . . . . . . . . . . . . . . 315 section 21. mechanical specifications . . . . . . . . . . . . . . . . 325 section 22. ordering information. . . . . . . . . . . . . . . . . . . . . 329 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of sections technical data MC68HC908JB16 ? rev. 1.0 6 list of sections motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola table of contents 7 technical data ? MC68HC908JB16 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.6.1 power supply pins (v dd , v ss ) . . . . . . . . . . . . . . . . . . . . . . .34 1.6.2 voltage regulator output pin (v reg ). . . . . . . . . . . . . . . . . . 34 1.6.3 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 35 1.6.4 external reset pin (rst) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.5 external interrupt pins (irq, pte4/d ? ) . . . . . . . . . . . . . . . .35 1.6.6 cgm power supply pins (v dda , v ssa0 , v ssa1 ) . . . . . . . . . 36 1.6.7 cgm voltage regulator out (v rega0 ). . . . . . . . . . . . . . . . . 36 1.6.8 cgm voltage regulator in (v rega1 ) . . . . . . . . . . . . . . . . . . 36 1.6.9 external filter capacitor pins (cgmxfc1, cgmxfc2) . . .36 1.6.10 cgm clock output pins (cgmout1, cgmout2) . . . . . . . 36 1.6.11 port a input/output (i/o) pins (pta7/kba7 ? pta0/kba0). .36 1.6.12 port c i/o pins (ptc1/rxd, ptc0/txd) . . . . . . . . . . . . . . . 37 1.6.13 port d i/o pins (ptd5 ? ptd0) . . . . . . . . . . . . . . . . . . . . . . . 37 1.6.14 port e i/o pins (pte4/d ? , pte3/d+, pte2/t2ch01, pte1/t1ch01, pte0/tclk). . . . . . . . . . . . . . . . . . . . . . 37 section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . .41 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data MC68HC908JB16 ? rev. 1.0 8 table of contents motorola 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . .42 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 section 3. random-access memory (ram) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 section 4. flash memory 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 4.5 flash block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.8 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.8.1 flash block protect register . . . . . . . . . . . . . . . . . . . . . . .66 4.9 rom-resident routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 4.9.1 variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.9.2 erase routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 4.9.3 program routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.9.4 verify routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 section 5. configuration register (config) 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.4 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC908JB16 ? rev. 1.0 technical data motorola table of contents 9 section 6. central processor unit (cpu) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . .80 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . .82 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 6.7 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 section 7. oscillator (osc) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.3 oscillator external connections . . . . . . . . . . . . . . . . . . . . . . . . 94 7.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 95 7.4.2 crystal amplifier output pin (osc1) . . . . . . . . . . . . . . . . . . 95 7.4.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 95 7.4.4 crystal output frequency signal (oscxclk). . . . . . . . . . . 95 7.4.5 clock doubler out (oscdclk) . . . . . . . . . . . . . . . . . . . . . . 95 7.4.6 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data MC68HC908JB16 ? rev. 1.0 10 table of contents motorola 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.6 oscillator during break mode. . . . . . . . . . . . . . . . . . . . . . . . . . 96 section 8. system integration module (sim) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . 100 8.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.3.2 clock startup from por or lvi reset . . . . . . . . . . . . . . . . 101 8.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . .101 8.4 reset and system initialization. . . . . . . . . . . . . . . . . . . . . . . . 101 8.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.4.2 active resets from internal sources . . . . . . . . . . . . . . . . . 103 8.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.4.2.2 computer operating properly (cop) reset. . . . . . . . . . 105 8.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . 106 8.4.2.6 universal serial bus (usb) reset . . . . . . . . . . . . . . . . . 106 8.4.2.7 registers values after different resets. . . . . . . . . . . . . 106 8.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 8.5.1 sim counter during power-on reset . . . . . . . . . . . . . . . . 107 8.5.2 sim counter during stop mode recovery . . . . . . . . . . . . . 108 8.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . .108 8.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.6.2 interrupt status registers. . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.6.2.1 interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . 112 8.6.2.2 interrupt status register 2 . . . . . . . . . . . . . . . . . . . . . . . 114 8.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 8.6.5 status flag protection in break mode . . . . . . . . . . . . . . . .114 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC908JB16 ? rev. 1.0 technical data motorola table of contents 11 8.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 8.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 8.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 8.8.1 sim break status register (sbsr) . . . . . . . . . . . . . . . . . . 118 8.8.2 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . 119 8.8.3 sim break flag control register (sbfcr) . . . . . . . . . . . .120 section 9. monitor rom (mon) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 9.4.3 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 9.4.4 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 9.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.5.1 extended security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 section 10. timer interface module (tim) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 10.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 144 10.5.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . .145 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data MC68HC908JB16 ? rev. 1.0 12 table of contents motorola 10.5.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . .145 10.5.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . 146 10.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . .147 10.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 10.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 10.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10.9.1 tim clock pin (pte0/tclk) . . . . . . . . . . . . . . . . . . . . . . . 151 10.9.2 tim channel i/o pins (pte1/t1ch01:pte2/t2ch01) . . . 151 10.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.10.1 tim status and control register . . . . . . . . . . . . . . . . . . . .152 10.10.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 10.10.3 tim counter modulo registers . . . . . . . . . . . . . . . . . . . . . 155 10.10.4 tim channel status and control registers . . . . . . . . . . . .156 10.10.5 tim channel registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 section 11. universal serial bus module (usb) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.5.1 usb protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.5.1.1 sync pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 11.5.1.2 packet identifier field . . . . . . . . . . . . . . . . . . . . . . . . . .171 11.5.1.3 address field (addr) . . . . . . . . . . . . . . . . . . . . . . . . . .172 11.5.1.4 endpoint field (endp). . . . . . . . . . . . . . . . . . . . . . . . . .172 11.5.1.5 cyclic redundancy check (crc) . . . . . . . . . . . . . . . . . 172 11.5.1.6 end-of-packet (eop) . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 11.5.2 reset signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC908JB16 ? rev. 1.0 technical data motorola table of contents 13 11.5.3 suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.5.4 resume after suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.5.4.1 host initiated resume . . . . . . . . . . . . . . . . . . . . . . . . . .175 11.5.4.2 usb reset signalling. . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.5.4.3 remote wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.5.5 low-speed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 11.6 clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 11.7 hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.1 voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.2 usb transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.2.1 output driver characteristics . . . . . . . . . . . . . . . . . . . . . 178 11.7.2.2 low speed (1.5 mbps) driver characteristics . . . . . . . . 178 11.7.2.3 receiver data jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11.7.2.4 data source jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11.7.2.5 data signal rise and fall time . . . . . . . . . . . . . . . . . . .180 11.7.3 usb control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.8.1 usb address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.8.2 usb interrupt register 0 . . . . . . . . . . . . . . . . . . . . . . . . . .183 11.8.3 usb interrupt register 1 . . . . . . . . . . . . . . . . . . . . . . . . . .185 11.8.4 usb interrupt register 2 . . . . . . . . . . . . . . . . . . . . . . . . . .188 11.8.5 usb control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 11.8.6 usb control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 11.8.7 usb control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11.8.8 usb control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 11.8.9 usb control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.8.10 usb status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 11.8.11 usb status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 11.8.12 usb endpoint 0 data registers . . . . . . . . . . . . . . . . . . . . . 198 11.8.13 usb endpoint 1 data registers . . . . . . . . . . . . . . . . . . . . . 199 11.8.14 usb endpoint 2 data registers . . . . . . . . . . . . . . . . . . . . . 200 11.9 usb interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 11.9.1 usb end-of-transaction interrupt . . . . . . . . . . . . . . . . . . .201 11.9.1.1 receive control endpoint 0 . . . . . . . . . . . . . . . . . . . . . .202 11.9.1.2 transmit control endpoint 0 . . . . . . . . . . . . . . . . . . . . .204 11.9.1.3 transmit endpoint 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data MC68HC908JB16 ? rev. 1.0 14 table of contents motorola 11.9.1.4 transmit endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 11.9.1.5 receive endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 11.9.2 resume interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 11.9.3 end-of-packet interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 section 12. serial communications interface module (sci) 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.5.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 12.5.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 12.5.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 12.5.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . 215 12.5.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.5.2.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.5.2.5 inversion of transmitted output. . . . . . . . . . . . . . . . . . . 217 12.5.2.6 transmitter interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 217 12.5.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 12.5.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 12.5.3.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . .218 12.5.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 12.5.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 12.5.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .222 12.5.3.6 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12.5.3.7 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 12.5.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 12.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 12.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 12.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 12.7 sci during break module interrupts. . . . . . . . . . . . . . . . . . . . 228 12.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC908JB16 ? rev. 1.0 technical data motorola table of contents 15 12.8.1 txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 12.8.2 rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 12.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 12.9.1 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 12.9.2 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 12.9.3 sci control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 12.9.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 12.9.5 sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 12.9.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 12.9.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 section 13. clock generator module (cgm) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 13.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.3.1 reference frequency source (oscxclk) . . . . . . . . . . . .250 13.3.2 voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . 250 13.3.3 reference divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.3.4 vco frequency divider . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.3.5 phase detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.3.6 phase detector filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.3.7 lock detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 13.4.1 cgm power supply pins (v dda , v ssa0 , v ssa1 ) . . . . . . . . 252 13.4.2 cgm1 voltage regulator out (v rega0 ) . . . . . . . . . . . . . . .252 13.4.3 cgm2 voltage regulator in (v rega1 ) . . . . . . . . . . . . . . . . 252 13.4.4 external filter capacitor pins (cgmxfc1, cgmxfc2) . . 253 13.4.5 cgm clock output pins (cgmout1, cgmout2) . . . . . . 253 13.5 cgmxfc external connections . . . . . . . . . . . . . . . . . . . . . . . 253 13.6 cgmout external connections. . . . . . . . . . . . . . . . . . . . . . . 254 13.7 calculation of vco frequency . . . . . . . . . . . . . . . . . . . . . . . . 254 13.8 programming the pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 13.9 cgm i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data MC68HC908JB16 ? rev. 1.0 16 table of contents motorola 13.9.1 bandwidth control register . . . . . . . . . . . . . . . . . . . . . . . . 256 13.9.2 vco control register (pvcr) . . . . . . . . . . . . . . . . . . . . . .256 13.9.3 vco and reference divider select registers high . . . . . . 257 13.9.4 vco divider select register low . . . . . . . . . . . . . . . . . . .258 13.9.5 reference divider select register low . . . . . . . . . . . . . . . 259 13.9.6 phase detector control register (pdcr) . . . . . . . . . . . . . 260 13.10 pre-defined vco output frequency settings . . . . . . . . . . . .260 13.11 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 13.11.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 13.11.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 section 14. input/output (i/o) ports 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 14.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 14.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 14.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 267 14.4 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 14.4.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 14.4.2 data direction register c. . . . . . . . . . . . . . . . . . . . . . . . . . 270 14.5 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 14.5.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 14.5.2 data direction register d. . . . . . . . . . . . . . . . . . . . . . . . . . 273 14.6 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 14.6.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 14.6.2 data direction register e. . . . . . . . . . . . . . . . . . . . . . . . . . 277 14.7 port options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 14.7.1 port option control register . . . . . . . . . . . . . . . . . . . . . . . 279 section 15. external interrupt (irq) 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC908JB16 ? rev. 1.0 technical data motorola table of contents 17 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 15.5 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 15.6 pte4/d ? pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 15.7 irq module during break interrupts . . . . . . . . . . . . . . . . . . .285 15.8 irq status and control register . . . . . . . . . . . . . . . . . . . . . . 286 15.9 irq option control register. . . . . . . . . . . . . . . . . . . . . . . . . . 287 section 16. keyboard interrupt module (kbi) 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 16.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 16.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 16.6 keyboard initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 16.7 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 16.7.1 keyboard status and control register. . . . . . . . . . . . . . . . 294 16.7.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 295 16.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 16.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 16.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 16.9 keyboard module during break interrupts . . . . . . . . . . . . . . .296 section 17. computer operating properly (cop) 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 17.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 17.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data MC68HC908JB16 ? rev. 1.0 18 table of contents motorola 17.4.1 oscdclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 17.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 17.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 17.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 17.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 17.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 17.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 17.4.8 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . 300 17.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 17.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 17.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 17.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 17.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 17.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 17.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . .302 section 18. low-voltage inhibit (lvi) 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 18.4.1 low v dd detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 18.4.2 low v reg detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 18.5 lvi control and configuration . . . . . . . . . . . . . . . . . . . . . . . . 305 18.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 18.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 18.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 section 19. break module (brk) 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC908JB16 ? rev. 1.0 technical data motorola table of contents 19 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 19.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 19.4.1 flag protection during break interrupts . . . . . . . . . . . . . . .310 19.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 310 19.4.3 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . 310 19.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 310 19.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310 19.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 19.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 19.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 19.6.1 break status and control register. . . . . . . . . . . . . . . . . . .311 19.6.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . .312 19.6.3 sim break status register . . . . . . . . . . . . . . . . . . . . . . . . . 312 19.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . .314 section 20. electrical specifications 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 20.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . .316 20.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 317 20.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 20.6 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 318 20.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 20.8 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 20.9 timer interface module characteristics . . . . . . . . . . . . . . . . . 320 20.10 usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 320 20.11 usb low-speed source electrical characteristics . . . . . . . . 321 20.12 usb signaling levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 20.13 cgm electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 322 20.14 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 324 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data MC68HC908JB16 ? rev. 1.0 20 table of contents motorola section 21. mechanical specifications 21.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 21.3 32-pin low-profile quad flat pack (lqfp) . . . . . . . . . . . . . . 326 21.4 28-pin small outline integrated circuit (soic) . . . . . . . . . . . 327 section 22. ordering information 22.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 22.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola list of figures 21 technical data ? MC68HC908JB16 list of figures figure title page 1-1 MC68HC908JB16 mcu block diagram . . . . . . . . . . . . . . . . . . 32 1-2 32-pin lqfp pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . .33 1-3 28-pin soic pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1-4 power supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1-5 regulator supply capacitor configuration . . . . . . . . . . . . . . . .35 2-1 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2-2 control, status, and data registers . . . . . . . . . . . . . . . . . . . . . 44 4-1 flash i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . 60 4-2 flash control register (flcr) . . . . . . . . . . . . . . . . . . . . . . . 61 4-3 flash programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . 65 4-4 flash block protect register (flbpr). . . . . . . . . . . . . . . . . . 66 4-5 flash block protect start address . . . . . . . . . . . . . . . . . . . . . 66 5-1 configuration register (config). . . . . . . . . . . . . . . . . . . . . . .72 6-1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6-3 index register (h:x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 6-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . 80 7-1 oscillator external connections . . . . . . . . . . . . . . . . . . . . . . . . 94 8-1 sim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8-2 sim i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8-3 sim clock signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8-4 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures technical data MC68HC908JB16 ? rev. 1.0 22 list of figures motorola figure title page 8-5 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8-6 sources of internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8-7 por recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8-8 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8-9 interrupt entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8-10 interrupt recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 8-11 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . . . . 111 8-12 interrupt status register 1 (int1). . . . . . . . . . . . . . . . . . . . . .112 8-13 interrupt status register 2 (int2). . . . . . . . . . . . . . . . . . . . . .114 8-14 wait mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 8-15 wait recovery from interrupt or break . . . . . . . . . . . . . . . . . . 116 8-16 wait recovery from internal reset. . . . . . . . . . . . . . . . . . . . . 116 8-17 stop mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 8-18 stop mode recovery from interrupt or break . . . . . . . . . . . . . 117 8-19 sim break status register (sbsr) . . . . . . . . . . . . . . . . . . . . 118 8-20 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . . . 119 8-21 sim break flag control register (sbfcr) . . . . . . . . . . . . . . 120 9-1 monitor mode circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9-2 low-voltage monitor mode entry flowchart. . . . . . . . . . . . . . 127 9-3 monitor data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9-4 break transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9-5 read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9-6 write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9-7 stack pointer at monitor mode entry . . . . . . . . . . . . . . . . . . .134 9-8 monitor mode entry timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10-1 tim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10-2 tim i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10-3 pwm period and pulse width . . . . . . . . . . . . . . . . . . . . . . . . 146 10-4 tim status and control register (tsc) . . . . . . . . . . . . . . . . . 152 10-5 tim counter registers high (tcnth) . . . . . . . . . . . . . . . . . . 154 10-6 tim counter registers low (tcntl) . . . . . . . . . . . . . . . . . . . 155 10-7 tim counter modulo register high (tmodh) . . . . . . . . . . . .155 10-8 tim counter modulo register low (tmodl) . . . . . . . . . . . . . 155 10-9 tim channel 0 status and control register (tsc0) . . . . . . . 156 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures MC68HC908JB16 ? rev. 1.0 technical data motorola list of figures 23 figure title page 10-10 tim channel 1 status and control register (tsc1) . . . . . . . 156 10-11 chxmax latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 10-12 tim channel 0 register high (tch0h) . . . . . . . . . . . . . . . . . 160 10-13 tim channel 0 register low (tch0l) . . . . . . . . . . . . . . . . . . 160 10-14 tim channel 1 register high (tch1h) . . . . . . . . . . . . . . . . . 160 10-15 tim channel 1 register low (tch1l) . . . . . . . . . . . . . . . . . . 160 11-1 usb i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . .164 11-2 usb block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11-3 supported transaction types per endpoint. . . . . . . . . . . . . . 169 11-4 supported usb packet types . . . . . . . . . . . . . . . . . . . . . . . . 170 11-5 sync pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11-6 sop, sync signaling, and voltage levels . . . . . . . . . . . . . . . 171 11-7 eop transaction voltage levels . . . . . . . . . . . . . . . . . . . . . . 173 11-8 eop width timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 11-9 external low-speed device configuration . . . . . . . . . . . . . . .176 11-10 regulator electrical connections . . . . . . . . . . . . . . . . . . . . . . 177 11-11 receiver characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 11-12 differential input sensitivity range. . . . . . . . . . . . . . . . . . . . . 179 11-13 data jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 11-14 data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . 180 11-15 usb address register (uaddr) . . . . . . . . . . . . . . . . . . . . . . 182 11-16 usb interrupt register 0 (uir0) . . . . . . . . . . . . . . . . . . . . . . . 183 11-17 usb interrupt register 1 (uir1) . . . . . . . . . . . . . . . . . . . . . . . 185 11-18 usb interrupt register 2 (uir2) . . . . . . . . . . . . . . . . . . . . . . . 188 11-19 usb control register 0 (ucr0) . . . . . . . . . . . . . . . . . . . . . . . 189 11-20 usb control register 1 (ucr1) . . . . . . . . . . . . . . . . . . . . . . . 190 11-21 usb control register 2 (ucr2) . . . . . . . . . . . . . . . . . . . . . . . 191 11-22 usb control register 3 (ucr3) . . . . . . . . . . . . . . . . . . . . . . . 193 11-23 usb control register 4 (ucr4) . . . . . . . . . . . . . . . . . . . . . . . 195 11-24 usb status register 0 (usr0). . . . . . . . . . . . . . . . . . . . . . . . 196 11-25 usb status register 2 (usr1). . . . . . . . . . . . . . . . . . . . . . . . 197 11-26 usb endpoint 0 data registers (ue0d0 ? ue0d7). . . . . . . . .198 11-27 usb endpoint 1 data registers (ue1d0 ? ue1d7). . . . . . . . .199 11-28 usb endpoint 2 data registers (ue2d0 ? ue2d7). . . . . . . . .200 11-29 out token data flow for receive endpoint 0. . . . . . . . . . . . 202 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures technical data MC68HC908JB16 ? rev. 1.0 24 list of figures motorola figure title page 11-30 setup token data flow for receive endpoint 0 . . . . . . . . . 203 11-31 in token data flow for transmit endpoint 0 . . . . . . . . . . . . . 204 11-32 in token data flow for transmit endpoint 1 . . . . . . . . . . . . . 205 12-1 sci module block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 211 12-2 sci i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 12-3 sci data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 12-4 sci transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 12-5 sci receiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 219 12-6 receiver data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 12-7 slow data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 12-8 fast data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 12-9 sci control register 1 (scc1). . . . . . . . . . . . . . . . . . . . . . . . 230 12-10 sci control register 2 (scc2). . . . . . . . . . . . . . . . . . . . . . . .233 12-11 sci control register 3 (scc3). . . . . . . . . . . . . . . . . . . . . . . .235 12-12 sci status register 1 (scs1) . . . . . . . . . . . . . . . . . . . . . . . . 238 12-13 flag clearing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 12-14 sci status register 2 (scs2) . . . . . . . . . . . . . . . . . . . . . . . . 242 12-15 sci data register (scdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 12-16 sci baud rate register (scbr) . . . . . . . . . . . . . . . . . . . . . . 244 13-1 cgm i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . 248 13-2 cgm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 13-3 cgm power supply connection . . . . . . . . . . . . . . . . . . . . . . . 252 13-4 cgmxfc external connections . . . . . . . . . . . . . . . . . . . . . . . 253 13-5 cgmout external connections. . . . . . . . . . . . . . . . . . . . . . . 254 13-6 pll bandwidth control register (pbcr) . . . . . . . . . . . . . . . . 256 13-7 vco control register (pvcr) . . . . . . . . . . . . . . . . . . . . . . . . 256 13-8 pll1 n & r divider select register high (pnrh1) . . . . . . . .257 13-9 pll2 n & r divider select register high (pnrh2) . . . . . . . .257 13-10 pll1 n divider select register low (pnsl1) . . . . . . . . . . . .258 13-11 pll2 n divider select register low (pnsl2) . . . . . . . . . . . .258 13-12 pll1 r divider select register low (prsl1) . . . . . . . . . . . .259 13-13 pll2 r divider select register low (prsl2) . . . . . . . . . . . .259 13-14 phase detector control register (pdcr) . . . . . . . . . . . . . . . 260 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures MC68HC908JB16 ? rev. 1.0 technical data motorola list of figures 25 figure title page 14-1 i/o port register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 264 14-2 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . . .266 14-3 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . 267 14-4 port a i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 14-5 port c data register (ptc) . . . . . . . . . . . . . . . . . . . . . . . . . .269 14-6 data direction register c (ddrc) . . . . . . . . . . . . . . . . . . . . . 270 14-7 port c i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 14-8 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . . .272 14-9 data direction register d (ddrd) . . . . . . . . . . . . . . . . . . . . . 273 14-10 port d i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 14-11 port e data register (pte) . . . . . . . . . . . . . . . . . . . . . . . . . .275 14-12 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . . . 277 14-13 port e i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 14-14 port option control register (pocr). . . . . . . . . . . . . . . . . . . 279 15-1 irq module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .283 15-2 irq i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 283 15-3 irq status and control register (iscr) . . . . . . . . . . . . . . . . 286 15-4 irq option control register (iocr) . . . . . . . . . . . . . . . . . . .287 16-1 i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 16-2 keyboard module block diagram . . . . . . . . . . . . . . . . . . . . . .291 16-3 keyboard status and control register (kbscr) . . . . . . . . . . 294 16-4 keyboard interrupt enable register (kbier) . . . . . . . . . . . . . 295 17-1 cop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 17-2 configuration register (config). . . . . . . . . . . . . . . . . . . . . .300 17-3 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . .301 18-1 lvi module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 18-2 configuration register (config). . . . . . . . . . . . . . . . . . . . . .305 19-1 break module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 309 19-2 break module i/o register summary . . . . . . . . . . . . . . . . . . . 309 19-3 break status and control register (brkscr). . . . . . . . . . . . 311 19-4 break address register high (brkh) . . . . . . . . . . . . . . . . . . 312 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures technical data MC68HC908JB16 ? rev. 1.0 26 list of figures motorola figure title page 19-5 break address register low (brkl) . . . . . . . . . . . . . . . . . . . 312 19-6 sim break status register (sbsr) . . . . . . . . . . . . . . . . . . . . 313 19-7 sim break flag control register (sbfcr) . . . . . . . . . . . . . . 314 21-1 32-pin lqfp (case #873a) . . . . . . . . . . . . . . . . . . . . . . . . . .326 21-2 28-pin soic (case #751f). . . . . . . . . . . . . . . . . . . . . . . . . . . 327 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola list of tables 27 technical data ? MC68HC908JB16 list of tables table title page 1-1 summary of pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2-1 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 4-1 rom-resident routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 4-2 summary of flash routine variables . . . . . . . . . . . . . . . . . . 68 4-3 erase routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4-4 program routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4-5 verify routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6-1 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6-2 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8-1 sim module signal name conventions . . . . . . . . . . . . . . . . . .99 8-2 pin bit set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 8-3 registers not affected by normal reset. . . . . . . . . . . . . . . . . 107 8-4 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9-1 mode entry requirements and options . . . . . . . . . . . . . . . . . 126 9-2 monitor mode vector differences . . . . . . . . . . . . . . . . . . . . . .128 9-3 monitor baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . 129 9-4 read (read memory) command . . . . . . . . . . . . . . . . . . . . . 131 9-5 write (write memory) command. . . . . . . . . . . . . . . . . . . . . 132 9-6 iread (indexed read) command . . . . . . . . . . . . . . . . . . . . . 132 9-7 iwrite (indexed write) command . . . . . . . . . . . . . . . . . . . .133 9-8 readsp (read stack pointer) command . . . . . . . . . . . . . . .133 9-9 run (run user program) command . . . . . . . . . . . . . . . . . . . 134 9-10 monitor mode security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of tables technical data MC68HC908JB16 ? rev. 1.0 28 list of tables motorola table title page 10-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10-2 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 10-3 mode, edge, and level selection . . . . . . . . . . . . . . . . . . . . . .158 11-1 usb module pin name conventions . . . . . . . . . . . . . . . . . . .164 11-2 supported packet identifiers. . . . . . . . . . . . . . . . . . . . . . . . . . 171 12-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12-2 start bit verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 12-3 data bit recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 12-4 stop bit recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 12-5 character format selection . . . . . . . . . . . . . . . . . . . . . . . . . .232 12-6 sci baud rate prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 12-7 sci baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 12-8 sci baud rate selection examples . . . . . . . . . . . . . . . . . . . . 246 13-1 predefined programming setting for pll . . . . . . . . . . . . . . . . 260 14-1 port control register bits summary. . . . . . . . . . . . . . . . . . . . 265 14-2 port a pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 14-3 port c pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 14-4 port d pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 14-5 port e pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 16-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 22-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola general description 29 technical data ? MC68HC908JB16 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.6.1 power supply pins (v dd , v ss ) . . . . . . . . . . . . . . . . . . . . . . .34 1.6.2 voltage regulator output pin (v reg ). . . . . . . . . . . . . . . . . . 34 1.6.3 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 35 1.6.4 external reset pin (rst) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.5 external interrupt pins (irq, pte4/d ? ) . . . . . . . . . . . . . . . .35 1.6.6 cgm power supply pins (v dda , v ssa0 , v ssa1 ) . . . . . . . . . 36 1.6.7 cgm voltage regulator out (v rega0 ). . . . . . . . . . . . . . . . . 36 1.6.8 cgm voltage regulator in (v rega1 ) . . . . . . . . . . . . . . . . . . 36 1.6.9 external filter capacitor pins (cgmxfc1, cgmxfc2) . . .36 1.6.10 cgm clock output pins (cgmout1, cgmout2) . . . . . . . 36 1.6.11 port a input/output (i/o) pins (pta7/kba7 ? pta0/kba0). .36 1.6.12 port c i/o pins (ptc1/rxd, ptc0/txd) . . . . . . . . . . . . . . . 37 1.6.13 port d i/o pins (ptd5 ? ptd0) . . . . . . . . . . . . . . . . . . . . . . . 37 1.6.14 port e i/o pins (pte4/d ? , pte3/d+, pte2/t2ch01, pte1/t1ch01, pte0/tclk). . . . . . . . . . . . . . . . . . . . . . 37 1.2 introduction the MC68HC908JB16 is a member of the low-cost, high-performance m68hc08 family of 8-bit microcontroller units (mcus). the m68hc08 family is based on the customer-specified integrated circuit (csic) design strategy. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data MC68HC908JB16 ? rev. 1.0 30 general description motorola 1.3 features features of the MC68HC908JB16 mcu include the following: high-performance m68hc08 architecture fully upward-compatible object code with m6805, m146805, and m68hc05 families low-power design; fully static with stop and wait modes 6-mhz internal bus frequency 16,384 bytes of on-chip flash memory with security 1 feature 384 bytes of on-chip random access memory (ram) up to 21 general-purpose input/output (i/o) pins, including: ? 15 shared-function i/o pins ? 8-bit keyboard interrupt port ? 10ma high current drive for ps/2 connection on 2 pins (with usb module disabled) ? 1 dedicated i/o pin, with 25ma direct drive for infrared led (32-pin package) ? 6 dedicated i/o pins, with 25ma direct drive for infrared led on 2 pins and 10ma direct drive for normal led on 4 pins (28-pin package) two 16-bit, 2-channel timer interface modules (tim1 and tim2) with selectable input capture, output compare, pwm capability on each channel, and external clock input option (tclk) universal serial bus specification 2.0 low-speed functions: ? 1.5mbps data rate ? on-chip 3.3v regulator ? endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer ? endpoint 1 with 8-byte transmit buffer ? endpoint 2 with 8-byte transmit buffer and 8-byte receive buffer 1. no security feature is absolutely secure. however, motorola ? s strategy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description mcu block diagram MC68HC908JB16 ? rev. 1.0 technical data motorola general description 31 serial communications interface module (sci) dual clock generator modules (cgm) (32-pin package) in-circuit programming capability using usb communication or standard serial link on pta0 pin system protection features: ? optional computer operating properly (cop) reset ? optional low-voltage detection with reset ? illegal opcode detection with reset ? illegal address detection with reset master reset pin with internal pull-up and power-on reset irq interrupt pin with internal pull-up and schmitt-trigger input 32-pin low-profile quad flat pack (lqfp) and 28-pin small outline integrated circuit package (soic) features of the cpu08 include the following: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications third party c language support 1.4 mcu block diagram figure 1-1 shows the structure of the MC68HC908JB16. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data MC68HC908JB16 ? rev. 1.0 32 general description motorola figure 1-1. MC68HC908JB16 mcu block diagram system integration module 2-channel timer interface module 1 low voltage inhibit module computer operating properly module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes user flash memory ? 16,384 bytes user ram ? 384 bytes monitor rom ? 1,472 bytes user flash vectors ? 48 bytes power and internal pta ddra ddre pte internal bus usb module usb endpoint 0, 1, 2 ls usb transceiver break module oscillator ptc ddrc keyboard interrupt module power-on reset module (1) osc1 (1) osc2 (2) rst (3) irq v dd v ss v reg (3.3v) 2-channel timer interface module 2 serial communications interface module irq module dual clock generator module (5) cgmxfc1 (1), (5) cgmout1 (5) cgmxfc2 (1), (5) cgmout2 voltage regulators pte0/tclk (3) pte1/t1ch01 (3) pte2/t2ch01 (3) pte3/d+ (3), (4) pte4/d? (3), (4) ptc1/rxd (3) ptc0/txd (3) pta7/kba7 pta0/kba0 (1) pins have 3v logic. (2) pins have integrated pullup device. (3) pins have software configurable pull-up device. (4) pins are open-drain when configured as output. (5) pins available on 32-pin package only. : (3) (5) v dda (5) v ssa0 (5) v ssa1 (6) pins available on 28-pin package only. (5) v rega1 (3.3v) (5) v rega0 (3.3v) ddrd ptd ptd0 (4) ptd1 (4), (6) ptd2 (4), (6) ptd3 (4), (6) ptd4 (4), (6) ptd5 (4), (6) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments MC68HC908JB16 ? rev. 1.0 technical data motorola general description 33 1.5 pin assignments figure 1-2. 32-pin lqfp pin assignment figure 1-3. 28-pin soic pin assignment cgmxfc2 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 24 20 19 18 17 9 vss osc1 osc2 vreg vdd ptd0 pte1/t1ch01 pte3/d+ pta7/kba7 irq ptc0/txd pte4/d ? ptc1/rxd pta6/kba6 pta4/kba4 pta5/kba5 pta0/kba0 cgmout2 vssa1 pte0/tclk pta3/kba3 pte2/t2ch01 pta2/kba2 pta1/kba1 rst 23 22 21 cgmxfc1 vssa0 vrega0 vdda vrega1 cgmout1 pins not available on 32-pin package: ptd5 ptd4 ptd3 ptd2 ptd1 1 2 3 4 5 6 7 28 27 26 25 24 23 22 21 20 19 18 12 13 14 17 16 15 8 9 10 11 osc1 irq pta0/kba0 rst pta1/kba1 pta2/kba2 pta3/kba3 pte0/tclk pte2/t2ch01 pta4/kba4 pta5/kba5 pta6/kba6 pta7/kba7 ptd5 ptc1/rxd osc 2 vreg vdd ptd0 ptd1 ptd2 ptd3 ptd4 pte1/t1ch01 pte3/d+ pte4/d ? ptc0/txd vss pins not available on 28-pin package: cgmxfc1 cgmxfc2 cgmout1 cgmout2 vrega0 vrega1 vssa0 vssa1 vdda f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data MC68HC908JB16 ? rev. 1.0 34 general description motorola 1.6 pin functions description of pin functions are provided here. 1.6.1 power supply pins (v dd , v ss ) v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu as figure 1-4 shows. place the bypass capacitors as close to the mcu power pins as possible. use high-frequency-response ceramic capacitors for c bypass . c bulk are optional bulk current bypass capacitors for use in applications that require the port pins to source high current levels. figure 1-4. power supply bypassing 1.6.2 voltage regulator output pin (v reg ) v reg is the 3.3v output of the on-chip voltage regulator. v reg is used internally for the mcu operation and the usb data driver. it is also used to supply the voltage for the external pullup resistor required on the usb ? s d ? line. the v reg pin requires an external bulk capacitor 4.7 figure 1-5 shows. place the bypass capacitors as close to the v reg pin as possible. mcu c bulk c bypass 0.1 f + note: values shown are typical values. v dd v dd v ss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin functions MC68HC908JB16 ? rev. 1.0 technical data motorola general description 35 figure 1-5. regulator supply capacitor configuration 1.6.3 oscillator pins (osc1 and osc2) the osc1 and osc2 pins are the connections for the on-chip oscillator circuit. 1.6.4 external reset pin (rst ) a logic zero on the rst pin forces the mcu to a known start-up state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. the rst pin contains an internal pullup device to v dd . (see section 8. system integration module (sim) .) 1.6.5 external interrupt pins (irq , pte4/d ? ) irq is an asynchronous external interrupt pin. irq is also the pin to enter monitor mode. the irq pin contains a software configurable pullup device to v dd . pte4/d ? can be programmed to trigger the irq interrupt. (see section 15. external interrupt (irq) .) mcu v reg c regbulk c regbypass 0.1 f v ss + v reg > 4.7 f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data MC68HC908JB16 ? rev. 1.0 36 general description motorola 1.6.6 cgm power supply pins (v dda , v ssa0 , v ssa1 ) v dda is the power supply pin, v ssa0 and v ssa1 are the ground pins for the analog portion of the clock generator modules (cgms). connect v dda to the same voltage potential as v dd . connect v ssa0 and v ssa1 pins to the same voltage potential as v ss . decoupling of these pins should be as per the digital supply. 1.6.7 cgm voltage regulator out (v rega0 ) v rega0 is the 3.3v output of the second on-chip voltage regulator. v rega0 is used for cgm1 and cgm2 operation. decoupling of this pin should be as per the digital v reg . 1.6.8 cgm voltage regulator in (v rega1 ) v rega1 is the 3.3v input pin for cgm2. connect v rega1 directly to v rega0 . decoupling of v rega1 pin should be as per v rega0 . 1.6.9 external filter capacitor pins (cgmxfc1, cgmxfc2) cgmxfc1 and cgmxfc2 are external capacitor connections for the respective cgms. 1.6.10 cgm clock output pins (cgmout1, cgmout2) cgmout1 and cgmout2 are buffered vco outputs of the respective cgms. 1.6.11 port a input/output (i/o) pins (pta7/kba7 ? pta0/kba0 ) pta7/kba7 ? pta0/kba0 are general-purpose bidirectional i/o port pins. (see section 14. input/output (i/o) ports .) each pin contains a software configurable pullup device to v dd when the pin is configured as an input. (see 14.7 port options .) each pin can also be programmed as an external keyboard interrupt pin. (see section 16. keyboard interrupt module (kbi) .) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin functions MC68HC908JB16 ? rev. 1.0 technical data motorola general description 37 1.6.12 port c i/o pins (ptc1/rxd, ptc0/txd) port c is a 2-bit special function port that shares its pins with the sci module. (see section 14. input/output (i/o) ports .) each pin contains a software configurable pullup device to v dd when the pin is configured as an input. (see 14.7 port options .) 1.6.13 port d i/o pins (ptd5 ? ptd0) ptd5 ? ptd0 are general-purpose bidirectional i/o port pins; open-drain when configured as output. (see section 14. input/output (i/o) ports .) ptd5 ? ptc2 are software configurable to be 10ma sink pins for direct led connections. ptd1 ? ptd0 are software configurable to be 25ma sink pins for direct infrared led connections. (see 14.7 port options .) 1.6.14 port e i/o pins (pte4/d ? , pte3/d+, pte2/t2ch01, pte1/t1ch01, pte0/tclk) port e is a 5-bit special function port that shares two of its pins with the usb module and three of its pins with the two timer interface modules. each pte2 ? pte0 pin contains a software configurable pullup device to v dd when the pin is configured as an input or output. when the usb module is disabled, the pte4 and pte3 pins are general-purpose bidirectional i/o port pins with 10ma sink capability. each pin is open-drain when configured as an output; and each pin contains a software configurable 5k ? ? and pte3/d+ pins become the usb module d ? and d+ pins. the usb d ? pin contains a 1.5k ? section 10. timer interface module (tim) , section 11. universal serial bus module (usb) and section 14. input/output (i/o) ports .) note: any unused inputs and i/o ports should be tied to an appropriate logic level (either v dd or v ss ). although the i/o ports of the MC68HC908JB16 do not require termination, termination is recommended to reduce the possibility of static damage. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data MC68HC908JB16 ? rev. 1.0 38 general description motorola summary of the pin functions are provided in table 1-1 . table 1-1. summary of pin functions pin name pin description in/out voltage level v dd power supply. in 4.0 to 5.5v v ss power supply ground. out 0v v reg 3.3v regulated output from mcu. out v reg (3.3v) rst reset input, active low. with internal pull-up and schmitt trigger input. in/out v dd irq external irq pin; with programmable internal pull-up and schmitt trigger input. in v dd used for mode entry selection. in v reg to v tst osc1 crystal oscillator input. in v reg osc2 crystal oscillator output; inverting of osc1 signal. out v reg v dda (1) analog power supply. in 4.0 to 5.5v v ssa0 (1) v ssa1 (1) analog power supply ground. out 0v v rega0 (1) 3.3v regulated output from mcu. out v rega0 (3.3v) v rega1 (1) 3.3v input for cgm2. in v rega0 cgmxfc1 (1) cgm1 external filter capacitor connection. out v rega0 cgmxfc2 (1) cgm2 external filter capacitor connection. out v rega0 cgmout1 (1) cgm1 clock output. out v rega0 cgmout2 (1) cgm2 clock output. out v rega0 pta0/kba0 : pta7/kba7 8-bit general purpose i/o port. in/out v dd pins as keyboard interrupts, kba0 ? kba7 .in v dd each pin has programmable internal pullup when configured as input. in v dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin functions MC68HC908JB16 ? rev. 1.0 technical data motorola general description 39 ptc0/txd ptc1/rxd 2-bit general purpose i/o port. in/out v dd each pin has programmable internal pull-up device. in v dd ptc0 as txd of sci module. out v dd ptc1 as rxd of sci module. in v dd ptd0 ? ptd5 (2) 6-bit general purpose i/o port; open-drain when configured as output. in out v dd v reg or v dd ptd0 ? ptd1 have configurable 25ma sink for infrared led. out v reg or v dd ptd2 ? ptd5 have configurable 10ma sink for led. out v reg or v dd pte0/tclk pte1/t1ch01 pte2/t2ch01 pte0 ? pte2 are general purpose i/o lines. in/out v dd pte0 ? pte2 have programmable internal pullup when configured as input or output. in/out v dd pte0 as tclk of tim1 and tim2. in v dd pte1 as t1ch01 of tim1. in/out v dd pte2 as t2ch01 of tim2. in/out v dd pte3/d+ pte4/d ? pte3 ? pte4 general purpose i/o lines; open-drain when configured as output. in out v dd v reg or v dd pte3 ? pte4 have programmable internal pullup when configured as input. in v dd pte3 as d+ of usb module. in/out v reg pte4 as d ? of usb module. in/out v reg pte4 as additional irq interrupt. in v dd notes : 1. pin available on 32-pin package only. 2. ptd[5:1] pins available on 28-pin package only. table 1-1. summary of pin functions pin name pin description in/out voltage level f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data MC68HC908JB16 ? rev. 1.0 40 general description motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola memory map 41 technical data ? MC68HC908JB16 section 2. memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . .41 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . .42 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 2.2 introduction the cpu08 can address 64k-bytes of memory space. the memory map, shown in figure 2-1 , includes: 16,384 bytes of flash memory 384 bytes of random-access memory (ram) 48 bytes of user-defined vectors 1,024 + 448 bytes of monitor rom 2.3 unimplemented memory locations accessing an unimplemented location can cause an illegal address reset if illegal address resets are enabled. in the memory map ( figure 2-1 ) and in register figures in this document, unimplemented locations are shaded. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data MC68HC908JB16 ? rev. 1.0 42 memory map motorola 2.4 reserved memory locations accessing a reserved location can have unpredictable effects on mcu operation. in the figure 2-1 and in register figures in this document, reserved locations are marked with the word reserved or with the letter r. 2.5 input/output (i/o) section most of the control, status, and data registers are in the zero page area of $0000 ? $007f. additional i/o registers have these addresses: $fe00; sim break status register, sbsr $fe01; sim reset status register, srsr $fe02; reserved $fe03; sim break flag control register, sbfcr $fe04; interrupt status register 1, int1 $fe05; interrupt status register 2, int2 $fe06; reserved $fe07; reserved $fe08; flash control register, flcr $fe09; flash block protect register, flbpr $fe0a; reserved $fe0b; reserved $fe0c; break address register high, brkh $fe0d; break address register low, brkl $fe0e; break status and control register, brkscr $fe0f; reserved $ffff; cop control register, copctl data registers are shown in figure 2-2 . table 2-1 is a list of vector locations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC908JB16 ? rev. 1.0 technical data motorola memory map 43 $0000 figure 2-1. memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data MC68HC908JB16 ? rev. 1.0 44 memory map motorola addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 reserved read: rrrrrrrr write: reset: $0002 port c data register (ptc) read:000000 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: 0 0 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:0*0000000 * ddra7 bit is reset by por or lvi reset only. $0005 reserved read: rrrrrrrr write: reset: $0006 data direction register c (ddrc) read:000000 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) read: 0 0 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) read: 0 0 0 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 data direction register e (ddre) read: 0 0 0 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 1 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC908JB16 ? rev. 1.0 technical data motorola memory map 45 $000a timer 1 status and control register (t1sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $000b reserved read: rrrrrrrr write: reset: $000c timer 1 counter register high (t1cnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $000d timer 1 counter register low (t1cntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $000e timer 1 counter modulo register high (t1modh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 $000f timer 1 counter modulo register low (t1modl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 $0010 timer 1 channel 0 status and control register (t1sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0011 timer 1 channel 0 register high (t1ch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0012 timer 1 channel 0 register low (t1ch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0013 timer 1 channel 1 status and control register (t1sc1) read: ch1f ch1ie ch01ie ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 2 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data MC68HC908JB16 ? rev. 1.0 46 memory map motorola $0014 timer 1 channel 1 register high (t1ch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0015 timer 1 channel 1 register low (t1ch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0016 keyboard status and control register (kbscr) read:0000keyf0 imaskk modek write: ackk reset:00000000 $0017 keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $0018 usb interrupt register 2 (uir2) read:00000000 write: eopfr rstfr txd2fr rxd2fr tdx1fr resumfr txd0fr rxd0fr reset:00000000 $0019 usb control register 2 (ucr2) read: t2seq stall2 tx2e rx2e tp2siz3 tp2siz2 tp2siz1 tp2siz0 write: reset:00000000 $001a usb control register 3 (ucr3) read: tx1st 0 ostall0 istall0 0 pullen enable2 enable1 write: tx1str reset:000000*00 * pullen bit is reset by por or lvi reset only. $001b usb control register 4 (ucr4) read:00000 fusbo fdp fdm write: reset:00000000 $001c irq option control register (iocr) read:00000pte4if pte4ie irqpd write: reset:00000000 $001d port option control register (pocr) read: pte20p ptdldd ptdildd pte4p pte3p pcp r pap write: reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 3 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC908JB16 ? rev. 1.0 technical data motorola memory map 47 $001e irq status and control register (intscr) read:0000irqf0 imask mode write: ack reset:00000000 $001f configuration register (config) ? read: lvidr lvi5or3 urstd lvid ssrec coprs stop copd write: reset:0*0*0*0*0000 ? one-time writable register after each reset. * lvidr, lvi5or3, urstd, and lvid, are reset by por or lvi reset only. $0020 usb endpoint 0 data register 0 (ue0d0) read: ue0r07 ue0r06 ue0r05 ue0r04 ue0r03 ue0r02 ue0r01 ue0r00 write: ue0t07 ue0t06 ue0t05 ue0t04 ue0t03 ue0t02 ue0t01 ue0t00 reset: unaffected by reset $0021 usb endpoint 0 data register 1 (ue0d1) read: ue0r17 ue0r16 ue0r15 ue0r14 ue0r13 ue0r12 ue0r11 ue0r10 write: ue0t17 ue0t16 ue0t15 ue0t14 ue0t13 ue0t12 ue0t11 ue0t10 reset: unaffected by reset $0022 usb endpoint 0 data register 2 (ue0d2) read: ue0r27 ue0r26 ue0r25 ue0r24 ue0r23 ue0r22 ue0r21 ue0r20 write: ue0t27 ue0t26 ue0t25 ue0t24 ue0t23 ue0t22 ue0t21 ue0t20 reset: unaffected by reset $0023 usb endpoint 0 data register 3 (ue0d3) read: ue0r37 ue0r36 ue0r35 ue0r34 ue0r33 ue0r32 ue0r31 ue0r30 write: ue0t37 ue0t36 ue0t35 ue0t34 ue0t33 ue0t32 ue0t31 ue0t30 reset: unaffected by reset $0024 usb endpoint 0 data register 4 (ue0d4) read: ue0r47 ue0r46 ue0r45 ue0r44 ue0r43 ue0r42 ue0r41 ue0r40 write: ue0t47 ue0t46 ue0t45 ue0t44 ue0t43 ue0t42 ue0t41 ue0t40 reset: unaffected by reset $0025 usb endpoint 0 data register 5 (ue0d5) read: ue0r57 ue0r56 ue0r55 ue0r54 ue0r53 ue0r52 ue0r51 ue0r50 write: ue0t57 ue0t56 ue0t55 ue0t54 ue0t53 ue0t52 ue0t51 ue0t50 reset: unaffected by reset $0026 usb endpoint 0 data register 6 (ue0d6) read: ue0r67 ue0r66 ue0r65 ue0r64 ue0r63 ue0r62 ue0r61 ue0r60 write: ue0t67 ue0t66 ue0t65 ue0t64 ue0t63 ue0t62 ue0t61 ue0t60 reset: unaffected by reset $0027 usb endpoint 0 data register 7 (ue0d7) read: ue0r77 ue0r76 ue0r75 ue0r74 ue0r73 ue0r72 ue0r71 ue0r70 write: ue0t77 ue0t76 ue0t75 ue0t74 ue0t73 ue0t72 ue0t71 ue0t70 reset: unaffected by reset addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 4 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data MC68HC908JB16 ? rev. 1.0 48 memory map motorola $0028 usb endpoint 1 data register 0 (ue1d0) read: write: ue1t07 ue1t06 ue1t05 ue1t04 ue1t03 ue1t02 ue1t01 ue1t00 reset: unaffected by reset $0029 usb endpoint 1 data register 1 (ue1d1) read: write: ue1t17 ue1t16 ue1t15 ue1t14 ue1t13 ue1t12 ue1t11 ue1t10 reset: unaffected by reset $002a usb endpoint 1 data register 2 (ue1d2) read: write: ue1t27 ue1t26 ue1t25 ue1t24 ue1t23 ue1t22 ue1t21 ue1t20 reset: unaffected by reset $002b usb endpoint 1 data register 3 (ue1d3) read: write: ue1t37 ue1t36 ue1t35 ue1t34 ue1t33 ue1t32 ue1t31 ue1t30 reset: unaffected by reset $002c usb endpoint 1 data register 4 (ue1d4) read: write: ue1t47 ue1t46 ue1t45 ue1t44 ue1t43 ue1t42 ue1t41 ue1t40 reset: unaffected by reset $002d usb endpoint 1 data register 5 (ue1d5) read: write: ue1t57 ue1t56 ue1t55 ue1t54 ue1t53 ue1t52 ue1t51 ue1t50 reset: unaffected by reset $002e usb endpoint 1 data register 6 (ue1d6) read: write: ue1t67 ue1t66 ue1t65 ue1t64 ue1t63 ue1t62 ue1t61 ue1t60 reset: unaffected by reset $002f usb endpoint 1 data register 7 (ue1d7) read: write: ue1t77 ue1t76 ue1t75 ue1t74 ue1t73 ue1t72 ue1t71 ue1t70 reset: unaffected by reset $0030 usb endpoint 2 data register 0 (ue2d0) read: ue2r07 ue2r06 ue2r05 ue2r04 ue2r03 ue2r02 ue2r01 ue2r00 write: ue2t07 ue2t06 ue2t05 ue2t04 ue2t03 ue2t02 ue2t01 ue2t00 reset: unaffected by reset $0031 usb endpoint 2 data register 1 (ue2d1) read: ue2r17 ue2r16 ue2r15 ue2r14 ue2r13 ue2r12 ue2r11 ue2r10 write: ue2t17 ue2t16 ue2t15 ue2t14 ue2t13 ue2t12 ue2t11 ue2t10 reset: unaffected by reset addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 5 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC908JB16 ? rev. 1.0 technical data motorola memory map 49 $0032 usb endpoint 2 data register 2 (ue2d2) read: ue2r27 ue2r26 ue2r25 ue2r24 ue2r23 ue2r22 ue2r21 ue2r20 write: ue2t27 ue2t26 ue2t25 ue2t24 ue2t23 ue2t22 ue2t21 ue2t20 reset: unaffected by reset $0033 usb endpoint 2 data register 3 (ue2d3) read: ue2r37 ue2r36 ue2r35 ue2r34 ue2r33 ue2r32 ue2r31 ue2r30 write: ue2t37 ue2t36 ue2t35 ue2t34 ue2t33 ue2t32 ue2t31 ue2t30 reset: unaffected by reset $0034 usb endpoint 2 data register 4 (ue2d4) read: ue2r47 ue2r46 ue2r45 ue2r44 ue2r43 ue2r42 ue2r41 ue2r40 write: ue2t47 ue2t46 ue2t45 ue2t44 ue2t43 ue2t42 ue2t41 ue2t40 reset: unaffected by reset $0035 usb endpoint 2 data register 5 (ue2d5) read: ue2r57 ue2r56 ue2r55 ue2r54 ue2r53 ue2r52 ue2r51 ue2r50 write: ue2t57 ue2t56 ue2t55 ue2t54 ue2t53 ue2t52 ue2t51 ue2t50 reset: unaffected by reset $0036 usb endpoint 2 data register 6 (ue2d6) read: ue2r67 ue2r66 ue2r65 ue2r64 ue2r63 ue2r62 ue2r61 ue2r60 write: ue2t67 ue2t66 ue2t65 ue2t64 ue2t63 ue2t62 ue2t61 ue2t60 reset: unaffected by reset $0037 usb endpoint 2 data register 7 (ue2d7) read: ue2r77 ue2r76 ue2r75 ue2r74 ue2r73 ue2r72 ue2r71 ue2r70 write: ue2t77 ue2t76 ue2t75 ue2t74 ue2t73 ue2t72 ue2t71 ue2t70 reset: unaffected by reset $0038 usb address register (uaddr) read: usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 write: reset:0*0000000 * usben bit is reset by por or lvi reset only. $0039 usb interrupt register 0 (uir0) read: eopie suspnd txd2ie rxd2ie txd1ie 0 txd0ie rxd0ie write: reset:00000000 $003a usb interrupt register 1 (uir1) read: eopf rstf txd2f rxd2f txd1f resumf txd0f rxd0f write: reset:00000000 $003b usb control register 0 (ucr0) read: t0seq 0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 6 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data MC68HC908JB16 ? rev. 1.0 50 memory map motorola $003c usb control register 1 (ucr1) read: t1seq stall1 tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset:00000000 $003d usb status register 0 (usr0) read: r0seq setup 0 0 rp0siz3 rp0siz2 rp0siz1 rp0siz0 write: reset: unaffected by reset $003e usb status register 1 (usr1) read: r2seq txack txnak txstl rp2siz3 rp2siz2 rp2siz1 rp2siz0 write: reset:u0 0 0uuuu $003f unimplemented read: write: $0040 timer 2 status and control register (t2sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0041 reserved read: rrrrrrrr write: reset: $0042 timer 2 counter register high (t2cnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $0043 timer 2 counter register low (t2cntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $0044 timer 2 counter modulo register high (t2modh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 $0045 timer 2 counter modulo register low (t2modl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 7 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC908JB16 ? rev. 1.0 technical data motorola memory map 51 $0046 timer 2 channel 0 status and control register (t2sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0047 timer 2 channel 0 register high (t2ch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0048 timer 2 channel 0 register low (t2ch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0049 timer 2 channel 1 status and control register (t2sc1) read: ch1f ch1ie ch01ie ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $004a timer 2 channel 1 register high (t2ch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $004b timer 2 channel 1 register low (t2ch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $004c reserved read: rrrrrrrr write: reset: $004d reserved read: rrrrrrrr write: reset: $004e reserved read: rrrrrrrr write: reset: $004f reserved read: rrrrrrrr write: reset: addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 8 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data MC68HC908JB16 ? rev. 1.0 52 memory map motorola $0050 reserved read: rrrrrrrr write: reset: $0051 pll bandwidth control register (pbwc) read: r lock1 r pllon1 r lock2 rpllon2 write: reset:0000 $0052 vco control register (pvcr) read: vco_7 vco_6 vco_5 vco_4 vco_3 vco_2 vco_1 vco_0 write: reset:00110000 $0053 pll1 n & r divider select register high (pnrh1) read: vds1_11 vds1_10 vds1_9 vds1_8 00 rds1_9 rds1_8 write: reset:00100000 $0054 pll1 n divider select register low (pnsl1) read: vds1_7 vds1_6 vds1_5 vds1_4 vds1_3 vds1_2 vds1_1 vds1_0 write: reset:01111101 $0055 pll1 r divider select register low (prsl1) read: rds1_7 rds1_6 rds1_5 rds1_4 rds1_3 rds1_2 rds1_1 rds1_0 write: reset:10010000 $0056 pll2 n & r divider select register high (pnrh2) read: vds2_11 vds2_10 vds2_9 vds2_8 00 rds2_9 rds2_8 write: reset:00100000 $0057 pll2 n divider select register low (pnsl1) read: vds2_7 vds2_6 vds2_5 vds2_4 vds2_3 vds2_2 vds2_1 vds2_0 write: reset:01111101 $0058 pll2 r divider select register low (prsl2) read: rds2_7 rds2_6 rds2_5 rds2_4 rds2_3 rds2_2 rds2_1 rds2_0 write: reset:10010000 $0059 phase detector control register (pdcr) read: phd_7 phd_6 phd_5 phd_4 phd_3 phd_2 phd_1 phd_0 write: reset:10010000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 9 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC908JB16 ? rev. 1.0 technical data motorola memory map 53 $005a sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $005b sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $005c sci control register 3 (scc3) read: r8 t8 dmare dmate orie neie feie peie write: reset: uu 000000 $005d sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset:11000000 $005e sci status register 2 (scs2) read:000000bkfrpf write: reset:00000000 $005f sci data register (scdr) read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: uuuuuuuu $0060 sci baud rate register (scbr) read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:0000 000 $0061 reserved read: rrrrrrrr write: reset: $0062 reserved read: rrrrrrrr write: reset: $0063 reserved read: rrrrrrrr write: reset: addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 10 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data MC68HC908JB16 ? rev. 1.0 54 memory map motorola $0064 to $007f unimplemented read: write: reset: $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 0 note: writing a logic 0 clears sbsw. $fe01 sim reset status register (srsr) read: por pin cop ilop ilad usb lvi 0 write: por:10000000 $fe02 reserved read: rrrrrrrr write: reset: $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 reserved read: rrrrrrrr write: reset: $fe07 reserved read: rrrrrrrr write: reset: addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 11 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC908JB16 ? rev. 1.0 technical data motorola memory map 55 $fe08 flash control register (flcr) read:0000 hven mass erase pgm write: reset:00000000 $fe09 flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 $fe0a reserved read: rrrrrrrr write: reset: $fe0b reserved read: rrrrrrrr write: reset: $fe0c break address high register (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address low register (brkl) read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 $ffff cop control register (copctl) read: low byte of reset vector write: clears cop counter (any value) reset: unaffected by reset addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 12 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data MC68HC908JB16 ? rev. 1.0 56 memory map motorola . table 2-1. vector addresses vector priority vector address vector lowest if14 $ffe0 keyboard vector (high) $ffe1 keyboard vector (low) if13 $ffe2 sci transmit vector (high) $ffe3 sci transmit vector (low) if12 $ffe4 sci receive vector (high) $ffe5 sci receive vector (low) if11 $ffe6 sci error vector (high) $ffe7 sci error vector (low) if10 $ffe8 tim2 overflow vector (high) $ffe9 tim2 overflow vector (low) if9 $ffea tim2 channel 0 and 1 vector (high) $ffeb tim2 channel 0 and 1 vector (low) if8 $ffec tim2 channel 1 vector (high) $ffed tim2 channel 1 vector (low) if7 $ffee tim2 channel 0 vector (high) $ffef tim2 channel 0 vector (low) if6 $fff0 tim1 overflow vector (high) $fff1 tim1 overflow vector (low) if5 $fff2 tim1 channel 0 and 1 vector (high) $fff3 tim1 channel 0 and 1 vector (low) if4 $fff4 tim1 channel 1 vector (high) $fff5 tim1 channel 1 vector (low) if3 $fff6 tim1 channel 0 vector (high) $fff7 tim1 channel 0 vector (low) if2 $fff8 irq vector (high) $fff9 irq vector (low) if1 $fffa usb vector (high) $fffb usb vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) highest $ffff reset vector (low) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola random-access memory (ram) 57 technical data ? MC68HC908JB16 section 3. random-access memory (ram) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2 introduction this section describes the 384 bytes of ram (random-access memory). 3.3 functional description addresses $0080 through $01ff are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64k-byte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 128 bytes of ram. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and user data or code. when the stack pointer is moved from its reset location at $00ff out of page zero, direct addressing mode instructions can efficiently access all page zero ram locations. page zero ram, therefore, provides ideal locations for frequently accessed global variables. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. note: for m6805 compatibility, the h register is not stacked. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . random-access memory (ram) technical data MC68HC908JB16 ? rev. 1.0 58 random-access memory (ram) motorola during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note: be careful when using nested subroutines. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola flash memory 59 technical data ? MC68HC908JB16 section 4. flash memory 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 4.5 flash block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.8 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.8.1 flash block protect register . . . . . . . . . . . . . . . . . . . . . . .66 4.9 rom-resident routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 4.9.1 variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.9.2 erase routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 4.9.3 program routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.9.4 verify routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.2 introduction this section describes the operation of the embedded flash memory. this memory can be read, programmed, and erased from a single external supply. the program and erase operations are enabled through the use of an internal charge pump. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory technical data MC68HC908JB16 ? rev. 1.0 60 flash memory motorola 4.3 functional description the flash memory consists of an array of 16,384 bytes for user memory plus a block of 48 bytes for user interrupt vectors. an erased bit reads as logic 1 and a programmed bit reads as a logic 0. the flash memory is block erasable. the minimum erase block size is 512 bytes. program and erase operation operations are facilitated through control bits in flash control register (flcr).the address ranges for the flash memory are shown as follows: $ba00 ? $f9ff (user memory, 16,384 bytes) $ffd0 ? $ffff (user interrupt vectors, 48 bytes) programming tools are available from motorola. contact your local motorola representative for more information. note: a security feature prevents viewing of the flash contents. 1 addr.register name bit 7654321bit 0 $fe08 flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 $fe09 flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 = unimplemented figure 4-1. flash i/o register summary 1. no security feature is absolutely secure. however, motorola ? s strategy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory flash control register MC68HC908JB16 ? rev. 1.0 technical data motorola flash memory 61 4.4 flash control register the flash control register (flcr) controls flash program and erase operation. hven ? high voltage enable bit this read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. it can only be set if either pgm=1 or erase=1 and the sequence for erase or program/verify is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit this read/write bit configures the memory for mass erase operation or block erase operation when the erase bit is set. 1 = mass erase operation selected 0 = block erase operation selected erase ? erase control bit this read/write bit configures the memory for erase operation. this bit and the pgm bit should not be set to 1 at the same time. 1 = erase operation selected 0 = erase operation not selected pgm ? program control bit this read/write bit configures the memory for program operation. this bit and the erase bit should not be set to 1 at the same time. 1 = program operation selected 0 = program operation not selected address: $fe08 bit 7654321bit 0 read: 0000 hven mass erase pgm write: reset:00000000 = unimplemented figure 4-2. flash control register (flcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory technical data MC68HC908JB16 ? rev. 1.0 62 flash memory motorola 4.5 flash block erase operation use the following procedure to erase a block of flash memory. a block consists of 512 consecutive bytes starting from addresses $x000, $x200, $x400, $x600, $x800, $xa00, $xc00 or $xe00. the 48-byte user interrupt vectors area also forms a block. any block within the 16k bytes user memory area ($ba00 ? $f9ff) can be erased alone. note: the 48-byte user interrupt vectors, $ffd0 ? $ffff, cannot be erased by the block erase operation because of security reasons. mass erase is required to erase this block. 1. set the erase bit and clear the mass bit in the flash control register. 2. write any data to any flash address within the address range of the block to be erased. 3. wait for a time, t nvs (5 note: programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory flash mass erase operation MC68HC908JB16 ? rev. 1.0 technical data motorola flash memory 63 4.6 flash mass erase operation use the following procedure to erase the entire flash memory: 1. set both the erase bit and the mass bit in the flash control register. 2. write any data to any flash address within the address range $ffd0 ? $ffff. 3. wait for a time, t nvs (5 note: programming and erasing of flash locations cannot be performed by executing code from the flash memory; the code must be executed from ram. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory technical data MC68HC908JB16 ? rev. 1.0 64 flash memory motorola 4.7 flash program operation programming of the flash memory is done on a row basis. a row consists of 64 consecutive bytes starting from addresses $xx00, $xx40, $xx80 or $xxc0. the procedure for programming a row of the flash memory is outlined below: 1. set the pgm bit. this configures the memory for program operation and enables the latching of address and data for programming. 2. write any data to any flash address within the address range of the row to be programmed. 3. wait for a time, t nvs (5 note: programming and erasing of flash locations cannot be performed by executing code from the flash memory; the code must be executed from ram. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. do not exceed t prog maximum. see 20.14 flash memory characteristics . figure 4-3 shows a flowchart representation for programming the flash memory. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory flash program operation MC68HC908JB16 ? rev. 1.0 technical data motorola flash memory 65 figure 4-3. flash programming flowchart set hven bit write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash address change (step 6 to step 6), or must not exceed the maximum programming time, t prog max. the time between the last flash address programmed to clearing pgm bit (step 6 to step 9) note: 1 2 3 4 5 6 7 9 10 11 12 algorithm for programming a row (64 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory technical data MC68HC908JB16 ? rev. 1.0 66 flash memory motorola 4.8 flash protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. this protection is done by use of a flash block protect register (flbpr). the flbpr determines the range of the flash memory which is to be protected. the range of the protected area starts from a location defined by flbpr and ends to the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or program operations. note: when the flbpr is cleared (all 0 ? s), the entire flash memory is protected from being programmed and erased. when all the bits are set, the entire flash memory is accessible for program and erase. 4.8.1 flash block protect register the flash block protect register is implemented as an 8-bit i/o register. the 7 bits of the 8-bit content of this register determine the starting location of the protected range within the flash memory. bpr[7:0] ? flash block protect register bit 7 to bit 0 bpr[7:1] represent bits [15:9] of a 16-bit memory address; bits [8:0] are logic 0 ? s. figure 4-5. flash block protect start address address: $fe09 bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 figure 4-4. flash block protect register (flbpr) 16-bit memory address start address of flash block protect 000000000 bpr[7:1] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory rom-resident routines MC68HC908JB16 ? rev. 1.0 technical data motorola flash memory 67 bpr0 is used only for bpr[7:0] = $ff, for no block protection. the resultant 16-bit address is used for specifying the start address of the flash memory for block protection. the flash is protected from this start address to the end of flash memory, at $ffff. with this mechanism, the protect start address can be x000, x200, x400, x600, x800, xa00, xc00, or xe00 within the flash memory. examples of protect start address: 4.9 rom-resident routines rom-resident routines can be called by a program running in user mode or in monitor mode (see section 9. monitor rom (mon) ) for flash programming, erasing, and verifying. the range of the flash memory must be unprotected (see 4.8 flash protection ) before calling the erase or programming routine. bpr[7:0] start of address of protect range $00 to $ba the entire flash memory is protected. $bc ( 1011 1100 ) $bc00 ( 1011 1100 0000 0000) $be ( 1011 1110 ) $be00 ( 1011 1110 0000 0000) $c0 ( 1100 0000 ) $c000 ( 1100 0000 0000 0000) $c2 ( 1100 0010 ) $c200 ( 1100 0010 0000 0000) and so on... $fe $ffd0 ? $ffff (user vectors) $ff the entire flash memory is not protected. note: the end address of the protected range is always $ffff. table 4-1. rom-resident routines routine name call address description verify $fc03 flash verify routine erase $fc06 flash mass or block erase routine program $fc09 flash program routine f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory technical data MC68HC908JB16 ? rev. 1.0 68 flash memory motorola 4.9.1 variables the rom-resident routines use three variables: ctrlbyt, cpuspd and laddr; and one data buffer. the minimum size of the data buffer is one byte and the maximum size is 64 bytes. cpuspd must be set before calling the erase or programming routines, and should be set to four times the value of the cpu internal bus speed in mhz. for example: for cpu speed of 6mhz, cpuspd should be set to 24. 4.9.2 erase routine the erase routine erases the entire or a block of flash memory. the routine does not check for a blank range before or after erase. note: a block erase cannot be performed on the last block of flash memory (user vector at $ffd0) ? $ffff). table 4-2. summary of flash routine variables variable address description ctrlbyt $0088 control byte for setting mass or block erase. cpuspd $0089 timing adjustment for different cpu speeds. laddr $008a ? $008b last flash address to be programmed. databuf $0100 ? $013f data buffer for programming and verifying. table 4-3. erase routine routine erase calling address $fc06 stack use 5 bytes input cpuspd ? cpu speed hx ? contains any address in the range to be erased ctrlbyt ? mass or block erase mass erase if bit 6 = 1 block erase if bit 6 = 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory rom-resident routines MC68HC908JB16 ? rev. 1.0 technical data motorola flash memory 69 4.9.3 program routine the program routine programs a range of addresses in flash memory, which does not have to be on page boundaries, either at the begin or end address. 4.9.4 verify routine the verify routine reads and verifies a range of flash memory. table 4-4. program routine routine program calling address $fc09 stack use 7 bytes input cpuspd ? cpu speed hx ? flash start address to be programmed laddr ? flash end address to be programmed databuf ? contains the data to be programmed table 4-5. verify routine routine verify calling address $fc03 stack use 6 bytes input hx ? flash start address to be verified laddr ? flash end address to be verified databuf ? contains the data to be verified output c bit ? c bit is set if verify passes databuf ? contains the data in the range of the flash memory f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory technical data MC68HC908JB16 ? rev. 1.0 70 flash memory motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola configuration register (config) 71 technical data ? MC68HC908JB16 section 5. configuration register (config) 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.4 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 5.2 introduction this section describes the configuration register, config. the configuration register enables or disables these options: low voltage inhibit (lvi) module control and voltage trip point selection usb reset stop mode recovery time (2048 or 4096 oscdclk cycles) cop timeout period (2 18 ? 2 4 or 2 13 ? 2 4 oscdclk cycles) stop instruction computer operating properly module (cop) 5.3 functional description the configuration register is used in the initialization of various options. the configuration register can be written once after each reset. all of the configuration register bits are cleared during reset. since the various options affect the operation of the mcu, it is recommended that this register be written immediately after reset. the configuration register is located at $001f. the configuration register may be read at anytime. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) technical data MC68HC908JB16 ? rev. 1.0 72 configuration register (config) motorola 5.4 configuration register lvidr ? lvi disable bit for v reg lvidr disables the lvi circuit for v reg . (see section 18. low- voltage inhibit (lvi) .) 1 = lvi circuit for v reg disabled 0 = lvi circuit for v reg enabled note: there is no lvi circuit for v rega . lvi5or3 ? lvi trip point voltage select bit for v dd lvi5or3 selects the trip point voltage of the lvi circuit for v dd . (see section 18. low-voltage inhibit (lvi) .) 1 = lvi trips at 3.3v 0 = lvi trips at 2.4v urstd ? usb reset disable bit urstd disables the usb reset signal generating an internal reset to the cpu and internal registers. instead, it will generate an interrupt request to the cpu. (see section 11. universal serial bus module (usb) .) 1 = usb reset generates a usb interrupt request to cpu 0 = usb reset generates a chip reset lvid ? lvi disable bit for v dd lvid disables the lvi circuit for v dd . (see section 18. low-voltage inhibit (lvi) .) 1 = lvi circuit for v dd disabled 0 = lvi circuit for v dd enabled address: $001f bit 7654321bit 0 read: lvidr lvi5or3 urstd lvid ssrec coprs stop copd write: reset: 0* 0* 0* 0* 0 0 0 0 * lvidr, lvi5or3, urstd, and lvid bits are reset by por (power-on reset) or lvi reset only. figure 5-1. configuration register (config) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) configuration register MC68HC908JB16 ? rev. 1.0 technical data motorola configuration register (config) 73 ssrec ? short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 2048 oscdclk cycles instead of a 4096 oscdclk cycle delay. 1 = stop mode recovery after 2048 oscdclk cycles 0 = stop mode recovery after 4096 oscdclk cycles note: exiting stop mode by pulling reset will result in the long stop recovery. if using an external crystal oscillator, do not set the ssrec bit. coprs ? cop rate select bit coprs selects the cop timeout period. reset clears coprs. (see section 17. computer operating properly (cop) .) 1 = cop timeout period is 2 13 ? 2 4 oscdclk cycles 0 = cop timeout period is 2 18 ? 2 4 oscdclk cycles stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit copd disables the cop module. (see section 17. computer operating properly (cop) .) 1 = cop module disabled 0 = cop module enabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) technical data MC68HC908JB16 ? rev. 1.0 74 configuration register (config) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola central processor unit (cpu) 75 technical data ? MC68HC908JB16 section 6. central processor unit (cpu) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . .80 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . .82 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 6.7 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908JB16 ? rev. 1.0 76 central processor unit (cpu) motorola 6.2 introduction the m68hc08 cpu (central processor unit) is an enhanced and fully object-code-compatible version of the m68hc05 cpu. the cpu08 reference manual (motorola document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 6.3 features feature of the cpu include: object code fully upward-compatible with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-register manipulation instructions 6-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable internal bus definition for extension of addressing range beyond 64-kbytes low-power stop and wait modes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers MC68HC908JB16 ? rev. 1.0 technical data motorola central processor unit (cpu) 77 6.4 cpu registers figure 6-1 shows the five cpu registers. cpu registers are not part of the memory map. figure 6-1. cpu registers 6.4.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two ? s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 6-2. accumulator (a) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908JB16 ? rev. 1.0 78 central processor unit (cpu) motorola 6.4.2 index register the 16-bit index register allows indexed addressing of a 64k-byte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, the cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. 6.4.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. bit 15 1413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 6-3. index register (h:x) bit 15 1413121110987654321 bit 0 read: write: reset:0000000011111111 figure 6-4. stack pointer (sp) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers MC68HC908JB16 ? rev. 1.0 technical data motorola central processor unit (cpu) 79 note: the location of the stack is arbitrary and may be relocated anywhere in ram. moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. 6.4.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. bit 15 1413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 6-5. program counter (pc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908JB16 ? rev. 1.0 80 central processor unit (cpu) motorola 6.4.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set permanently to logic 1. the following paragraphs describe the functions of the condition code register. v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add- with-carry (adc) operation. the half-carry flag is required for binary- coded decimal (bcd) arithmetic operations. the daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 bit 7654321bit 0 read: v11hinzc write: reset: x11x1xxx x = indeterminate figure 6-6. condition code register (ccr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers MC68HC908JB16 ? rev. 1.0 technical data motorola central processor unit (cpu) 81 i ? interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908JB16 ? rev. 1.0 82 central processor unit (cpu) motorola c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 6.5 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (motorola document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 6.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.6.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu during break interrupts MC68HC908JB16 ? rev. 1.0 technical data motorola central processor unit (cpu) 83 6.6.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the condition code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock. after exiting stop mode, the cpu clock begins running after the oscillator stabilization delay. 6.7 cpu during break interrupts if the break module is enabled, a break interrupt causes the cpu to execute the software interrupt instruction (swi) at the completion of the current cpu instruction. (see section 19. break module (brk) .) the program counter vectors to $fffc ? $fffd ($fefc ? $fefd in monitor mode). a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted. 6.8 instruction set summary table 6-1 provides a summary of the m68hc08 instruction set. 6.9 opcode map the opcode map is provided in table 6-2 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908JB16 ? rev. 1.0 84 central processor unit (cpu) motorola table 6-1. instruction set summary (sheet 1 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a ?? ? ??? ?? ? ??? ? m) ?????? imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x ? m) ?????? imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a ?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ? ?? ??? ? ?? ??? ?????? rel 24 rr 3 bclr n , opr clear bit n in m mn ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 c b0 b7 0 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map MC68HC908JB16 ? rev. 1.0 technical data motorola central processor unit (cpu) 85 bcs rel branch if carry bit set (same as blo) pc ?????? rel 25 rr 3 beq rel branch if equal pc ?????? rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc ?????? rel 90 rr 3 bgt opr branch if greater than (signed operands) pc ?????? rel 92 rr 3 bhcc rel branch if half carry bit clear pc ?????? rel 28 rr 3 bhcs rel branch if half carry bit set pc ?????? rel 29 rr 3 bhi rel branch if higher pc ?????? rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc ?????? rel 24 rr 3 bih rel branch if irq pin high pc ?????? rel 2f rr 3 bil rel branch if irq pin low pc ?????? rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc ) = ?????? rel 93 rr 3 blo rel branch if lower (same as bcs) pc ?????? rel 25 rr 3 bls rel branch if lower or same pc ?????? rel 23 rr 3 blt opr branch if less than (signed operands) pc ) = ?????? rel 91 rr 3 bmc rel branch if interrupt mask clear pc ?????? rel 2c rr 3 bmi rel branch if minus pc ?????? rel 2b rr 3 bms rel branch if interrupt mask set pc ?????? rel 2d rr 3 bne rel branch if not equal pc ?????? rel 26 rr 3 bpl rel branch if plus pc ?????? rel 2a rr 3 bra rel branch always pc ?????? rel 20 rr 3 table 6-1. instruction set summary (sheet 2 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908JB16 ? rev. 1.0 86 central processor unit (cpu) motorola brclr n , opr , rel branch if bit n in m clear pc ????? ? ?????? rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc ????? ? ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc ? 1; push (pch) sp ? 1 pc ?????? rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc ? (m) = $00 pc ? (m) = $00 pc ? (m) = $00 pc ? (m) = $00 pc ? (m) = $00 pc ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c ????? 0inh 98 1 cli clear interrupt mask i ?? 0 ??? inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m ?? 01 ? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 table 6-1. instruction set summary (sheet 3 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map MC68HC908JB16 ? rev. 1.0 technical data motorola central processor unit (cpu) 87 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ? ?? ??? ? s complement) m ? (m) a ? (m) x ? (m) m ? (m) m ? (m) m ? (m) 0 ?? ?? ? (m:m + 1) ? ?? ??? ? (m) ? ?? ??? ?? ??? ? 1 or m ? 1 or x ? 1 pc ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m ? 1 a ? 1 x ? 1 m ? 1 m ? 1 m ? 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a ???? ?? ?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 6-1. instruction set summary (sheet 4 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908JB16 ? rev. 1.0 88 central processor unit (cpu) motorola inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m ? ?? ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? 1 push (pch); sp ? 1 pc ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a ?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( ) ?? ?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x ?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ? ?? ??? ? ?? 0 ?? table 6-1. instruction set summary (sheet 5 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map MC68HC908JB16 ? rev. 1.0 technical data motorola central processor unit (cpu) 89 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination ?? ?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a ? 0 ??? 0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two ? s complement) m ? (m) = $00 ? (m) a ? (a) = $00 ? (a) x ? (x) = $00 ? (x) m ? (m) = $00 ? (m) m ? (m) = $00 ? (m) ? ?? ??? ?????? inh 9d 1 nsa nibble swap a a ?????? inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a ?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp ? 1 ?????? inh 87 2 pshh push h onto stack push (h); sp ? 1 ?????? inh 8b 2 pshx push x onto stack push (x); sp ? 1 ?????? inh 89 2 pula pull a from stack sp ( ) ?????? inh 86 2 pulh pull h from stack sp ( ) ?????? inh 8a 2 pulx pull x from stack sp ( ) ?????? inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ? ?? ??? ? ?? ??? ?????? inh 9c 1 table 6-1. instruction set summary (sheet 6 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908JB16 ? rev. 1.0 90 central processor unit (cpu) motorola rti return from interrupt sp ?????? ; ( ?????? inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a ? (m) ? (c) ? ?? ??? ????? 1inh 99 1 sei set interrupt mask i ?? 1 ??? inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m ?? ?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) ?? ?? ? dir 35 dd 4 stop enable irq pin; stop oscillator i ?? 0 ??? inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m ?? ?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a ? (m) ? ?? ??? table 6-1. instruction set summary (sheet 7 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map MC68HC908JB16 ? rev. 1.0 technical data motorola central processor unit (cpu) 91 swi software interrupt pc ? 1; push (pch) sp ? 1; push (x) sp ? 1; push (a) sp ? 1; push (ccr) sp ? 1; i ?? 1 ??? inh 83 9 tap transfer a to ccr ccr ?????? ?????? inh 97 1 tpa transfer ccr to a a ?????? inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ?? ?? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x ?????? inh 95 2 txa transfer x to a a ?????? inh 9f 1 txs transfer h:x to sp (sp) ? 1 ?????? inh 94 2 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with post increment addressing mode rr relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing sp1 stack pointer, 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct destination addressing mode | logical or imm immediate addressing mode ? ( ) negation (two ? s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode ? ? not affected table 6-1. instruction set summary (sheet 8 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908JB16 ? rev. 1.0 92 central processor unit (cpu) motorola table 6-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789 abcd9ede9eef 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3 ext 4 sub 3ix2 5 sub 4 sp2 3 sub 2ix1 4 sub 3sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3 ext 4 cmp 3ix2 5 cmp 4 sp2 3 cmp 2ix1 4 cmp 3sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3 ext 4 sbc 3ix2 5 sbc 4 sp2 3 sbc 2ix1 4 sbc 3sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3 ext 4 cpx 3ix2 5 cpx 4 sp2 3 cpx 2ix1 4 cpx 3sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3sp1 3 lsr 1ix 2 tap 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3 ext 4 and 3ix2 5 and 4 sp2 3 and 2ix1 4 and 3sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3 ext 4 bit 3ix2 5 bit 4 sp2 3 bit 2ix1 4 bit 3sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3 ext 4 lda 3ix2 5 lda 4 sp2 3 lda 2ix1 4 lda 3sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3sp1 3 asr 1ix 2 psha 1inh 1 tax 1inh 2 ais 2imm 3 sta 2dir 4 sta 3 ext 4 sta 3ix2 5 sta 4 sp2 3 sta 2ix1 4 sta 3sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3 ext 4 eor 3ix2 5 eor 4 sp2 3 eor 2ix1 4 eor 3sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3 ext 4 adc 3ix2 5 adc 4 sp2 3 adc 2ix1 4 adc 3sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3 ext 4 ora 3ix2 5 ora 4 sp2 3 ora 2ix1 4 ora 3sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3 ext 4 add 3ix2 5 add 4 sp2 3 add 2ix1 4 add 3sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3 ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3 ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3 ext 4 ldx 3ix2 5 ldx 4 sp2 3 ldx 2ix1 4 ldx 3sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3 ext 4 stx 3ix2 5 stx 4 sp2 3 stx 2ix1 4 stx 3sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola oscillator (osc) 93 technical data ? MC68HC908JB16 section 7. oscillator (osc) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.3 oscillator external connections . . . . . . . . . . . . . . . . . . . . . . . . 94 7.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 95 7.4.2 crystal amplifier output pin (osc1) . . . . . . . . . . . . . . . . . . 95 7.4.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 95 7.4.4 crystal output frequency signal (oscxclk). . . . . . . . . . . 95 7.4.5 clock doubler out (oscdclk) . . . . . . . . . . . . . . . . . . . . . . 95 7.4.6 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.6 oscillator during break mode. . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.2 introduction the oscillator circuit is designed for use with crystals or ceramic resonators. the oscillator circuit generates the crystal clock signal, oscxclk, and passes through a clock doubler to produce oscdclk. this clock doubler clock is further divided by two before being passed on to the system integration module (sim) for bus clock generation. figure 7-1 shows the structure of the oscillator. the oscillator requires various external components. the MC68HC908JB16 operates from a nominal 12mhz crystal, providing a 6mhz internal bus clock. the 12mhz clock is required for various modules, such as the cgms and usb. the clock doubler clock, oscdclk, is used as the base clock for the cop module. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) technical data MC68HC908JB16 ? rev. 1.0 94 oscillator (osc) motorola 7.3 oscillator external connections in its typical configuration, the oscillator requires five external components. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 7-1 . this figure shows only the logical representation of the internal components and may not represent actual circuitry. the oscillator configuration uses five components: crystal, x 1 (nominally 12mhz) fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (not required for 12mhz) figure 7-1. oscillator external connections the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be required for all ranges of operation, especially with high-frequency crystals. refer to the crystal manufacturer ? s data for more information. c1 c2 simoscen oscdclk x1 r s * * r s can be 0 (shorted) when used with mcu from sim oscout to cgm to sim clock doubler 2 to cop, sci osc1 osc2 r b 12 mhz higher frequency crystals. refer to manufacturer ? s data. oscxclk 2 to usb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) i/o signals MC68HC908JB16 ? rev. 1.0 technical data motorola oscillator (osc) 95 7.4 i/o signals the following paragraphs describe the oscillator input/output (i/o) signals. 7.4.1 crystal amplifier input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. 7.4.2 crystal amplifier output pin (osc1) the osc2 pin is the output of the crystal oscillator inverting amplifier. 7.4.3 oscillator enable signal (simoscen) the simoscen signal comes from the system integration module (sim) and enables the oscillator. 7.4.4 crystal output frequency signal (oscxclk) oscxclk is the crystal oscillator output signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 7-1 shows only the logical relation of oscxclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of oscxclk is unknown and may depend on the crystal and other external factors. also, the frequency and amplitude of oscxclk can be unstable at startup. 7.4.5 clock doubler out (oscdclk) oscdclk is the clock doubler output signal. it runs at twice the speed of the crystal (f xclk ) and comes from the clock doubler circuit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) technical data MC68HC908JB16 ? rev. 1.0 96 oscillator (osc) motorola 7.4.6 oscillator out (oscout) oscout is the divide-by-two signal after the clock doubler circuit. it runs at the same speed as oscxclk, at crystal frequency (f xclk ). this signal goes to the sim, which generates the mcu clocks. oscout will be divided-by-two again in the sim and results in the internal bus frequency being one half of the crystal frequency. 7.5 low-power modes the wait and stop instructions put the mcu in low-power- consumption standby modes. 7.5.1 wait mode the wait instruction has no effect on the oscillator logic. oscxclk continues to drive to the mcu. 7.5.2 stop mode the stop instruction disables the oscxclk output. 7.6 oscillator during break mode the oscillator continues to drive oscxclk when the chip enters the break state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola system integration module (sim) 97 technical data ? MC68HC908JB16 section 8. system integration module (sim) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . 100 8.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.3.2 clock startup from por or lvi reset . . . . . . . . . . . . . . . . 101 8.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . .101 8.4 reset and system initialization. . . . . . . . . . . . . . . . . . . . . . . . 101 8.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.4.2 active resets from internal sources . . . . . . . . . . . . . . . . . 103 8.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.4.2.2 computer operating properly (cop) reset. . . . . . . . . . 105 8.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . 106 8.4.2.6 universal serial bus (usb) reset . . . . . . . . . . . . . . . . . 106 8.4.2.7 registers values after different resets. . . . . . . . . . . . . 106 8.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 8.5.1 sim counter during power-on reset . . . . . . . . . . . . . . . . 107 8.5.2 sim counter during stop mode recovery . . . . . . . . . . . . . 108 8.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . .108 8.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.6.2 interrupt status registers. . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.6.2.1 interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . 112 8.6.2.2 interrupt status register 2 . . . . . . . . . . . . . . . . . . . . . . . 114 8.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908JB16 ? rev. 1.0 98 system integration module (sim) motorola 8.6.5 status flag protection in break mode . . . . . . . . . . . . . . . .114 8.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 8.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 8.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 8.8.1 sim break status register (sbsr) . . . . . . . . . . . . . . . . . . 118 8.8.2 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . 119 8.8.3 sim break flag control register (sbfcr) . . . . . . . . . . . .120 8.2 introduction this section describes the system integration module (sim). together with the cpu, the sim controls all mcu activities. the sim is a system state controller that coordinates cpu and exception timing. a block diagram of the sim is shown in figure 8-1 . figure 8-2 is a summary of the sim i/o registers. the sim is responsible for: bus clock generation and control for cpu and peripherals ? stop/wait/reset/break entry and recovery ? internal clock control master reset control, including power-on reset (por) and cop timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture expandable to 128 interrupt sources table 8-1 shows the internal signal names used in this section. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) introduction MC68HC908JB16 ? rev. 1.0 technical data motorola system integration module (sim) 99 figure 8-1. sim block diagram table 8-1. sim module signal name conventions signal name description oscdclk clock doubler output which has twice the frequency of osc1 from the oscillator oscout the oscdclk frequency divided by two. this signal is again divided by two in the sim to generate the internal bus clocks. (bus clock = oscdclk 4 = oscxclk 2) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to oscillator) oscout (from osc) internal clocks master reset control reset pin logic illegal opcode (from cpu) illegal address (from address map decoders) cop timeout (from cop module) interrupt sources cpu interface reset control sim counter cop clock oscdclk (from osc) 2 usb reset (from usb module) lvi reset (from lvi module) vdd internal pull-up f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908JB16 ? rev. 1.0 100 system integration module (sim) motorola 8.3 sim bus clock control and generation the bus clock generator provides system clock signals for the cpu and peripherals on the mcu. the system clocks are generated from an incoming clock, oscout, as shown in figure 8-3 . figure 8-3. sim clock signals addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: see note reset: 0 note: writing a logic 0 clears sbsw. $fe01 sim reset status register (srsr) read: por pin cop ilop ilad usb lvi 0 write: por:10000000 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 figure 8-2. sim i/o register summary 2 bus clock generators sim sim counter from osc oscout oscdclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization MC68HC908JB16 ? rev. 1.0 technical data motorola system integration module (sim) 101 8.3.1 bus timing in user mode , the internal bus frequency is the oscillator frequency divided by two. 8.3.2 clock startup from por or lvi reset when the power-on reset (por) module or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inactive phase until after the 4096 oscdclk cycle por timeout has completed. the rst pin is driven low by the sim during this entire period. the ibus clocks start upon completion of the timeout. 8.3.3 clocks in stop mode and wait mode upon exit from stop mode by an interrupt, break, or reset, the sim allows oscdclk to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 2048 oscdclk cycles. (see 8.7.2 stop mode .) in wait mode, the cpu clocks are inactive. the sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. 8.4 reset and system initialization the mcu has the following reset sources: power-on reset module (por) external reset pin (rst ) computer operating properly module (cop) illegal opcode illegal address universal serial bus module (usb) low-voltage inhibit module (lvi) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908JB16 ? rev. 1.0 102 system integration module (sim) motorola all of these resets produce the vector $fffe ? ffff ($fefe ? feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 8.5 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr). (see 8.8 sim registers .) 8.4.1 external pin reset the rst pin circuit includes an internal pullup device. pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 oscdclk cycles, assuming that neither the por nor the lvi was the source of the reset. see table 8-2 for details. figure 8-4 shows the relative timing. figure 8-4. external reset timing table 8-2. pin bit set timing reset type number of cycles required to set pin por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l oscout f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization MC68HC908JB16 ? rev. 1.0 technical data motorola system integration module (sim) 103 8.4.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 oscdclk cycles to allow resetting of external peripherals. the internal reset signal irst continues to be asserted for an additional 32 cycles. (see figure 8-5 .) an internal reset can be caused by an illegal address, illegal opcode, cop timeout, lvi, the usb module or por. (see figure 8-6 . sources of internal reset .) note: for lvi or por resets, the sim cycles through 4096 oscdclk cycles during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 8-5 . figure 8-5. internal reset timing the cop reset is asynchronous to the bus clock. figure 8-6. sources of internal reset the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high oscdclk illegal address rst illegal opcode rst coprst por internal reset lvi usb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908JB16 ? rev. 1.0 104 system integration module (sim) motorola 8.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 oscdclk cycles. sixty-four oscdclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, the following events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables the oscillator to drive oscdclk. internal clocks to the cpu and modules are held inactive for 4096 oscdclk cycles to allow stabilization of the oscillator. the rst pin is driven low during the oscillator stabilization time. the por bit of the sim reset status register (srsr) is set and all other bits in the register are cleared. figure 8-7. por recovery porrst osc1 oscdclk oscout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization MC68HC908JB16 ? rev. 1.0 technical data motorola system integration module (sim) 105 8.4.2.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all internal reset sources. to prevent a cop module timeout, write any value to location $ffff. writing to location $ffff clears the cop counter and stages 12 through 5 of the sim counter. the sim counter output, which occurs at least every 2 12 ? 2 4 oscdclk cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout. the cop module is disabled if the rst pin or the irq pin is held at v tst while the mcu is in monitor mode. the cop module can be disabled only through combinational logic conditioned with the high voltage signal on the rst or the irq pin. this prevents the cop from becoming disabled as a result of external noise. during a break state, v tst on the rst pin disables the cop module. 8.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. if the stop enable bit, stop, in the mask option register is logic 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. 8.4.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. the sim actively pulls down the rst pin for all internal reset sources. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908JB16 ? rev. 1.0 106 system integration module (sim) motorola 8.4.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit module (lvi) asserts its output to the sim when the v dd or v reg voltage falls to the lvi reset voltage, v trip . the lvi bit in the sim reset status register (srsr) is set, and the external reset pin (rst ) is held low while the sim counter counts out 4096 oscdclk cycles. sixty-four oscdclk cycles later, the cpu is released from reset to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 8.4.2.6 universal serial bus (usb) reset the usb module will detect a reset signaled on the bus by the presence o f a n e x te n d e d s e0 at t h e u sb d a ta p i n s of a d e vic e . t h e m c u s e e i ng a single-ended 0 on its usb data inputs for more than 2.5 2.0 ). t h e device must be able to accept the device address via a set_address command (refer to section 9.4 of the universal serial bus specification rev. 2.0 ) no lat e r th a n 1 0 ms a f ter t h e r e set i s r e move d . usb reset can be disabled to generate an internal reset. it can be configured to generate irq interrupt. (see section 5. configuration register (config) .) note: usb reset is disabled when the usb module is disabled by clearing the usben bit of the usb address register (uaddr). 8.4.2.7 registers values after different resets some registers are reset by por or lvi reset only. table 8-3 shows the registers or register bits which are unaffected by normal resets. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim counter MC68HC908JB16 ? rev. 1.0 technical data motorola system integration module (sim) 107 8.5 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly module (cop). the sim counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of sim counters and supplies the clock for the cop module. the sim counter is clocked by the falling edge of oscdclk. 8.5.1 sim counter during power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initialized, it enables the oscillator to drive the bus clock state machine. table 8-3. registers not affected by normal reset bits registers after reset (except por or lvi) after por or lvi lvidr, lvi5or3, urstd, lvid config unaffected 0 usben uaddr unaffected 0 pullen ucr3 unaffected 0 all usr0, usr1 unaffected indeterminate all ue0d0 ? ue0d7 unaffected indeterminate all ue1d0 ? ue1d7 unaffected indeterminate all ue2d0 ? ue2d7 unaffected indeterminate all pta, ptc, ptd, and pte unaffected indeterminate ddra7 ddra unaffected 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908JB16 ? rev. 1.0 108 system integration module (sim) motorola 8.5.2 sim counter during stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt, break, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the configuration register (config). if the ssrec bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 oscdclk cycles down to 2048 oscdclk cycles. this is ideal for applications using canned oscillators that do not require long startup times from stop mode. external crystal applications should use the full stop recovery time, that is, with ssrec cleared in the configuration register (config). 8.5.3 sim counter and reset states external reset has no effect on the sim counter. (see 8.7.2 stop mode for details.) the sim counter is free-running after all reset states. (see 8.4.2 active resets from internal sources for counter control and internal reset recovery sequences.) 8.6 exception control normal, sequential program execution can be changed in three different ways: interrupts ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts 8.6.1 interrupts an interrupt temporarily changes the sequence of program execution to respond to a particular event. figure 8-8 flow charts the handling of system interrupts. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control MC68HC908JB16 ? rev. 1.0 technical data motorola system integration module (sim) 109 figure 8-8. interrupt processing no no no yes no no yes no yes yes (as many interrupts as exist on chip) i bit set? from reset break interrupt? i bit set? usb interrupt? irq interrupt? swi instruction? rti instruction? fetch next instruction. unstack cpu registers. stack cpu registers. set i bit. load pc with interrupt vector. execute instruction. yes yes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908JB16 ? rev. 1.0 110 system integration module (sim) motorola interrupts are latched and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced or the i bit is cleared. at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 8-9 shows interrupt entry timing. figure 8-10 shows interrupt recovery timing. figure 8-9 . interrupt entry figure 8-10. interrupt recovery module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1[15:8] pc ? 1 [7:0] opcode operand i bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control MC68HC908JB16 ? rev. 1.0 technical data motorola system integration module (sim) 111 8.6.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 8-11 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. figure 8-11 . interrupt recognition example the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908JB16 ? rev. 1.0 112 system integration module (sim) motorola 8.6.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 8.6.2 interrupt status registers the flags in the interrupt status registers identify maskable interrupt sources. table 8-4 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. 8.6.2.1 interrupt status register 1 if6 ? if1 ? interrupt flags 6 ? 1 these flags indicate the presence of interrupt requests from the sources shown in table 8-4 . 1 = interrupt request present 0 = no interrupt request present bit 1 and bit 0 ? always read 0 address: $fe04 bit 7654321bit 0 read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 r=reserved figure 8-12. interrupt status register 1 (int1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control MC68HC908JB16 ? rev. 1.0 technical data motorola system integration module (sim) 113 table 8-4. interrupt sources source flags mask (1) int register flag priority (2) vector address reset none none none 0 $fffe ? $ffff swi instruction none none none 0 $fffc ? $fffd usb reset interrupt rstf urstd if1 1 $fffa ? $fffb usb endpoint 0 transmit txd0f txd0ie usb endpoint 0 receive rxd0f rxd0ie usb endpoint 1 transmit txd1f txd1ie usb endpoint 2 transmit txd2f txd2ie usb endpoint 2 receive rxd2f rxd2ie usb end of packet eopf eopie usb resume interrupt resumf ? irq interrupt (irq , pte4) irqf, pte4if imask if2 2 $fff8 ? $fff9 tim 1 channel 0 ch0f ch0ie if3 3 $fff6 ? $fff7 tim 1 channel 1 ch1f ch1ie if4 4 $fff4 ? $fff5 tim 1 channel 0 & 1 ch0f & ch1f ch01ie if5 5 $fff2 ? $fff3 tim 1 overflow tof toie if6 6 $fff0 ? $fff1 tim 2 channel 0 ch0f ch0ie if7 7 $ffee ? $ffef tim 2 channel 1 ch1f ch1ie if8 8 $ffec ? $ffed tim 2 channel 0 & 1 ch0f & ch1f ch01ie if9 9 $ffea ? $ffeb tim 2 overflow tof toie if10 10 $ffe8 ? $ffe9 sci receiver overrun or orie if11 11 $ffe6 ? $ffe7 sci noise fag nf neie sci framing error fe feie sci parity error pe peie sci receiver full scrf scrie if12 12 $ffe4 ? $ffe5 sci input idle idle ilie sci transmitter empty scte sctie if13 13 $ffe2 ? $ffe3 sci transmission complete tc tcie keyboard interrupt keyf imaskk if14 14 $ffe0 ? $ffe1 notes : 1. the i bit in the condition code register is a global mask for all interrupt sources except the swi instruction. 2. highest priority = 0. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908JB16 ? rev. 1.0 114 system integration module (sim) motorola 8.6.2.2 interrupt status register 2 if14 ? if7 ? interrupt flags 14 ? 7 these flags indicate the presence of interrupt requests from the sources shown in table 8-4 . 1 = interrupt request present 0 = no interrupt request present 8.6.3 reset all reset sources always have equal and highest priority and cannot be arbitrated. 8.6.4 break interrupts the break module can stop normal program flow at a software- programmable break point by asserting its break interrupt output. (see section 19. break module (brk) .) the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 8.6.5 status flag protection in break mode the sim controls whether status flags contained in other modules can be cleared during break mode. the user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (bcfe) in the break flag control register (bfcr). address: $fe05 bit 7654321bit 0 read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 r=reserved figure 8-13. interrupt status register 2 (int2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) low-power modes MC68HC908JB16 ? rev. 1.0 technical data motorola system integration module (sim) 115 protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mode without losing status flag information. setting the bcfe bit enables the clearing mechanisms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a 2-step clearing mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 8.7 low-power modes executing the wait or stop instruction puts the mcu in a low-power- consumption mode for standby situations. the sim holds the cpu in a non-clocked state. the operation of each of these modes is described here. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 8.7.1 wait mode in wait mode, the cpu clocks are inactive while the peripheral clocks continue to run. figure 8-14 shows the timing for wait mode entry. a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wait instruction during which the interrupt occurred. in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (sbsr). if the cop disable bit, copd, in the configuration register (config) is logic 0, then the computer operating properly module (cop) is enabled and remains active in wait mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908JB16 ? rev. 1.0 116 system integration module (sim) motorola figure 8-14. wait mode entry timing figure 8-15 and figure 8-16 show the timing for wait recovery. figure 8-15. wait recovery from interrupt or break figure 8-16. wait recovery from internal reset 8.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset or break also causes an exit from stop mode. wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 oscdclk 32 cycles 32 cycles f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) low-power modes MC68HC908JB16 ? rev. 1.0 technical data motorola system integration module (sim) 117 the sim disables the oscillator signals (oscout and oscdclk) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ssrec bit in the configuration register (config). if ssrec is set, stop recovery is reduced from the normal delay of 4096 oscdclk cycles down to 2048. this is ideal for applications using canned oscillators that do not require long startup times from stop mode. note: external crystal applications should use the full stop recovery time by clearing the ssrec bit. a break interrupt during stop mode sets the sim break stop/wait bit (sbsw) in the sim break status register (sbsr). the sim counter is held in reset from the execution of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 8-17 shows stop mode entry timing. note: to minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0. figure 8-17. stop mode entry timing figure 8-18. stop mode recovery from interrupt or break stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction oscdclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908JB16 ? rev. 1.0 118 system integration module (sim) motorola 8.8 sim registers the sim has three memory mapped registers. sim break status register (sbsr) sim reset status register (srsr) sim break flag control register (sbfcr) 8.8.1 sim break status register (sbsr) the sim break status register contains a flag to indicate that a break caused an exit from stop or wait mode. sbsw ? sim break stop/wait this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. reset clears sbsw. 1 = stop mode or wait mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break state swi routine. the user can modify the return address on the stack by subtracting one from it. the following code is an example of this. writing 0 to the sbsw bit clears it. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note 1 reset: 0 note 1. writing a logic 0 clears sbsw. r = reserved figure 8-19. sim break status register (sbsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim registers MC68HC908JB16 ? rev. 1.0 technical data motorola system integration module (sim) 119 8.8.2 sim reset status register (srsr) this register contains seven flags that show the source of the last reset. all flag bits are cleared automatically following a read of the register. the register is initialized on power-up as shown with the por bit set and all other bits cleared. however, during a por or any other internal reset, the rst pin is pulled low. after the pin is released, it will be sampled 32 oscdclk cycles later. if the pin is not above a v ih at that time, then the pin bit in the srsr may be set in addition to whatever other bits are set. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register. address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad usb lvi 0 write: por:10000000 = unimplemented figure 8-20. sim reset status register (srsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908JB16 ? rev. 1.0 120 system integration module (sim) motorola pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address reset bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr usb ? universal serial bus reset bit 1 = last reset caused by the usb module 0 = por or read of srsr lvi ? low voltage inhibit reset bit 1 = last reset caused by the lvi circuit 0 = por or read of srsr 8.8.3 sim break flag control register (sbfcr) the sim break flag control register contains a bit that enables software to clear status bits while the mcu is in a break state. address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r = reserved figure 8-21. sim break flag control register (sbfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim registers MC68HC908JB16 ? rev. 1.0 technical data motorola system integration module (sim) 121 bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908JB16 ? rev. 1.0 122 system integration module (sim) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola monitor rom (mon) 123 technical data ? MC68HC908JB16 section 9. monitor rom (mon) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 9.4.3 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 9.4.4 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 9.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.5.1 extended security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 9.2 introduction this section describes the monitor rom (mon) and the monitor mode entry methods. the monitor rom allows complete testing of the mcu through a single-wire interface with host computer. this mode is also used for programming and erasing of flash memory in the mcu. monitor mode entry can be achieved without use of the higher voltage, v tst , as long as vector addresses $fffe and $ffff are blank, thus reducing the hardware requirements for in-circuit programming. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data MC68HC908JB16 ? rev. 1.0 124 monitor rom (mon) motorola 9.3 features features of the monitor rom include the following: normal user-mode pin functionality one pin dedicated to serial communication between monitor rom and host computer standard mark/space non-return-to-zero (nrz) communication with host computer execution of code in ram or flash flash memory security feature 1 flash memory programming interface 1,472 bytes monitor rom code size monitor mode entry without high voltage, v tst , if reset vector is blank ($fffe and $ffff contain $ff) standard monitor mode entry if high voltage, v tst , is applied to irq 9.4 functional description the monitor rom receives and executes commands from a host computer. figure 9-1 shows a example circuit used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute host-computer code in ram while most mcu pins retain normal operating mode functions. all communication between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pull-up resistor. 1. no security feature is absolutely secure. however, motorola ? s strategy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola monitor rom (mon) 125 figure 9-1. monitor mode circuit + + + + 10m ? mc145407 mc74hc125 hc908jb16 rst irq osc1 osc2 v ss pta0 v dd 10 k ? ? ? ? ? ? bus clock = f xclk 2 sw1: position b ? bus clock = f xclk 2. sw2: position c ? high-voltage entry to monitor mode. sw2: position d ? low-voltage entry to monitor mode (with blank reset vector). see section 20. for irq voltage level requirements. 3. sw3: position e ? osc1 directly driven by external oscillator. sw3: position f ? osc1 driven by crystal oscillator circuit. 10k ? ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data MC68HC908JB16 ? rev. 1.0 126 monitor rom (mon) motorola 9.4.1 entering monitor mode table 9-1 shows the pin conditions for entering monitor mode. as specified in the table, monitor mode may be entered after a por and will allow communication at 19200 baud provided one of the following sets of conditions is met: 1. if irq = v tst : ? external clock on osc1 is 12mhz ? pta3 = high ? pte3 = high 2. if $fffe & $ffff is blank (contains $ff): ? external clock on osc1 is 12mhz ? irq = v dd ? pte3 = high table 9-1. mode entry requirements and options irq $fffe and $ffff pte3 pta3 (1) pta2 pta1 pta0 external clock, f xclk bus frequency, f bus comments v tst (2) x 1 0 0 1 1 12 mhz 12 mhz (f xclk ) high-voltage entry to monitor mode. 38400 baud communication on pta0. cop disabled. v tst (2) x 11011 12mhz 6mhz (f xclk 2) high-voltage entry to monitor mode. 19200 baud communication on pta0. cop disabled. v dd blank (contain $ff) 1xxx1 12mhz 6mhz (f xclk 2) low-voltage entry to monitor mode. 19200 baud communication on pta0. cop disabled. v dd not blank 1xxxx 12mhz 6mhz (f xclk 2) enters user mode. if $fffe and $ffff is blank, mcu will encounter an illegal address reset. notes : 1. pta3 = 0: bypasses the divide-by-two prescaler to sim when using v tst for monitor mode entry. 2. see section 20. electrical specifications for v tst voltage level requirements. factory use only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola monitor rom (mon) 127 if v tst is applied to irq and pta3 is low upon monitor mode entry ( table 9-1 condition set 1), the bus frequency is a equal to the external clock, f xclk . if pta3 is high with v tst applied to irq upon monitor mode entry ( table 9-1 condition set 2), the bus frequency is a divide-by-two of the external clock. holding the pta3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if v tst is applied to irq . in this event, the oscout frequency is equal to the oscdclk frequency. entering monitor mode with v tst on irq , the cop is disabled as long as v tst is applied to either the irq or the rst . (see section 8. system integration module (sim) for more information on modes of operation.) if entering monitor mode without high voltage on irq and reset vector being blank ($fffe and $ffff) ( table 9-1 condition set 3, where irq applied voltage is v dd ), then all port a pin requirements and conditions, including the pta3 frequency divisor selection, are not in effect. this is to reduce circuit requirements when performing in-circuit programming. entering monitor mode with the reset vector being blank, the cop is always disabled regardless of the state of irq or the rst . figure 9-2. low-voltage monitor mode entry flowchart is vector blank? por triggered? normal user mode monitor mode execute monitor code no no yes yes por reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data MC68HC908JB16 ? rev. 1.0 128 monitor rom (mon) motorola figure 9-2 . shows a simplified diagram of the monitor mode entry when the reset vector is blank and irq = v dd . an external clock of 12mhz is required for a baud rate of 19200. enter monitor mode with the pin configuration shown in figure 9-1 by pulling rst low and then high. the rising edge of rst latches monitor mode. once monitor mode is latched, the values on the specified pins can change. once out of reset, the mcu waits for the host to send eight security bytes. (see 9.5 security .) after the security bytes, the mcu sends a break signal (10 consecutive logic zeros) to the host, indicating that it is ready to receive a command. the break signal also provides a timing reference to allow the host to determine the necessary baud rate. in monitor mode, the mcu uses different vectors for reset, swi (software interrupt), and break interrupt than those for user mode. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. table 9-2 is a summary of the vector differences between user mode and monitor mode. table 9-2. monitor mode vector differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) notes : 1. if the high voltage (v tst ) is removed from the irq pin or the rst pin, the sim asserts its cop enable output. the cop is a mask option enabled or disabled by the copd bit in the configuration register. $fefe $feff $fefc $fefd $fefc $fefd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola monitor rom (mon) 129 9.4.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. transmit and receive baud rates must be identical. figure 9-3. monitor data format 9.4.3 break signal a start bit (logic 0) followed by nine logic 0 bits is a break signal. when the monitor receives a break signal, it drives the pta0 pin high for the duration of two bits and then echoes back the break signal. figure 9-4. break transaction 9.4.4 baud rate the communication baud rate is dependant on oscillator frequency, f xclk . the state of pta3 also affects baud rate if entry to monitor mode is by irq =v tst . when pta3 is high, the divide by ratio is 625. if the pta3 pin is at logic zero upon entry into monitor mode, the divide by ratio is 312. bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo table 9-3. monitor baud rate selection monitor mode entry by: oscillator clock frequency, f clk pta3 baud rate irq = v tst 12 mhz 0 38400 bps 12 mhz 1 19200 bps blank reset vector, irq = v dd 12 mhz x 19200 bps f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data MC68HC908JB16 ? rev. 1.0 130 monitor rom (mon) motorola 9.4.5 commands the monitor rom uses the following commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) the monitor rom firmware echoes each received byte back to the pta0 pin for error checking. an 11-bit delay at the end of each command allows the host to send a break character to cancel the command. a delay of two bit times occurs before each echo and before read, iread, or readsp data is returned. the data returned by a read command appears after the echo of the last byte of the command. note: wait one bit time after each echo before sending the next byte. figure 9-5. read transaction read read echo from host address high address high address low address low data return 13, 2 11 4 4 notes: 2 = data return delay, 2 bit times 3 = cancel command delay, 11 bit times 4 = wait 1 bit time before sending next byte. 44 1 = echo delay, 2 bit times f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola monitor rom (mon) 131 figure 9-6. write transaction a brief description of each monitor mode command is given in table 9-4 through table 9-9 . table 9-4. read (read memory) command description read byte from memory operand specifies 2-byte address in high byte:low byte order data returned returns contents of specified address opcode $4a command sequence write write echo from host address high address high address low address low data data notes: 2 = cancel command delay, 11 bit times 3 = wait 1 bit time before sending next byte. 11 3 11 3 3 32, 3 1 = echo delay, 2 bit times read read echo sent to monitor address high address high address low data return address low f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data MC68HC908JB16 ? rev. 1.0 132 monitor rom (mon) motorola table 9-5. write (write memory) command description write byte to memory operand specifics 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence table 9-6. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand specifies 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence write write echo semt to monitor address high address high address low address low data data iread iread echo sent to monitor data return data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola monitor rom (mon) 133 note: a sequence of iread or iwrite commands can sequentially access a block of memory over the full 64k-byte memory map. table 9-7. iwrite (indexed write) command description write to last address accessed + 1 operand specifies single data byte data returned none opcode $19 command sequence iwrite iwrite echo sent to monitor data data table 9-8. readsp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence readsp readsp echo sent to monitor sp return sp high low f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data MC68HC908JB16 ? rev. 1.0 134 monitor rom (mon) motorola the mcu executes the swi and pshh instructions when it enters monitor mode. the run command tells the mcu to execute the pulh and rti instructions. before sending the run command, the host can modify the stacked cpu registers to prepare to run the host program. the readsp command returns the incremented stack pointer value, sp + 1. the high and low bytes of the program counter are at addresses sp+5 and sp+6. figure 9-7. stack pointer at monitor mode entry table 9-9. run (run user program) command description executes rti instruction operand none data returned none opcode $28 command sequence run run echo sent to monitor condition code register accumulator low byte of index register high byte of program counter low byte of program counter sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp sp + 6 high byte of index register sp + 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) security MC68HC908JB16 ? rev. 1.0 technical data motorola monitor rom (mon) 135 9.5 security a security feature discourages unauthorized reading of flash locations while in monitor mode. the host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6 ? $fffd. locations $fff6 ? $fffd contain user- defined data. note: do not leave locations $fff6 ? $fffd blank. for security reasons, program locations $fff6 ? $fffd. during monitor mode entry, the mcu waits after the power-on reset for the host to send the eight security bytes on pin pta0. if the received bytes match those at locations $fff6 ? $fffd, the host bypasses the security feature and can read all flash locations and execute code from flash. security remains bypassed until a power-on or an lvi reset occurs. if the reset was not a power-on or an lvi reset, security remains bypassed and security code entry is not required. (see figure 9-8 .) figure 9-8. monitor mode entry timing byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pta0 rst v dd 4096 + 32 oscdclk cycles 256 bus cycles (minimum) 1 4 1 1 2 1 break notes: 2 = data return delay, 2 bit times. 4 = wait 1 bit time before sending next byte. 4 from host from mcu 1 = echo delay, 2 bit times. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data MC68HC908JB16 ? rev. 1.0 136 monitor rom (mon) motorola upon power-on reset, if the received bytes of the security code do not match the data at locations $fff6 ? $fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading a flash location returns an invalid value and trying to execute code from flash causes an illegal address reset. after receiving the eight security bytes from the host, the mcu transmits a break character, signifying that it is ready to receive a command. note: the mcu does not transmit a break character until after the host sends the eight security bytes. to determine whether the security code entered is correct, check to see if bit 6 of ram address $80 is set. if it is, then the correct security code has been entered and flash can be accessed. if the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. after failing the security sequence, the flash module can also be mass erased by executing an erase routine that was downloaded into internal ram. the mass erase operation clears the security code locations so that all eight security bytes become $ff (blank). 9.5.1 extended security to further disable monitor mode functions, the monitor commands can be disabled by writing $7b to the flash location $ffd1 and $87 to the flash location $ffd0. table 9-10 shows the security settings that affect monitor mode operations. table 9-10. monitor mode security extended security monitor mode entry security monitor functions available not set bypassed read/write of ram and flash. failed read/write of ram. read of flash disabled. flash can only be mass erased. set bypassed read/write of ram and flash disabled. failed read/write of ram. read of flash disabled. flash can only be mass erased. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola timer interface module (tim) 137 technical data ? MC68HC908JB16 section 10. timer interface module (tim) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 10.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 144 10.5.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . .145 10.5.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . .145 10.5.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . 146 10.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . .147 10.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 10.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 10.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10.9.1 tim clock pin (pte0/tclk) . . . . . . . . . . . . . . . . . . . . . . . 151 10.9.2 tim channel i/o pins (pte1/t1ch01:pte2/t2ch01) . . . 151 10.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.10.1 tim status and control register . . . . . . . . . . . . . . . . . . . .152 10.10.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 10.10.3 tim counter modulo registers . . . . . . . . . . . . . . . . . . . . . 155 10.10.4 tim channel status and control registers . . . . . . . . . . . .156 10.10.5 tim channel registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data MC68HC908JB16 ? rev. 1.0 138 timer interface module (tim) motorola 10.2 introduction this section describes the timer interface (tim) module. the tim is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. figure 10-1 is a block diagram of the tim. this particular mcu has two timer interface modules which are denoted as tim1 and tim2. note: tim1 and tim2 each have channel 0 and channel 1 i/os connected together, forming a common i/o. because of this common i/o, both channels should not be simultaneously configured for output compare functions, otherwise, port pin contention will occur. 10.3 features features of the tim include: two input capture/output compare channels on one common i/o: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse-width-modulation (pwm) signal generation programmable tim clock input ? 7-frequency internal bus clock prescaler selection ? external tim clock input (bus frequency 2 maximum) free-running or modulo up-count operation toggle any channel pin on overflow tim counter stop and reset bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) pin name conventions MC68HC908JB16 ? rev. 1.0 technical data motorola timer interface module (tim) 139 10.4 pin name conventions the text that follows describes both timers, tim1 and tim2. the tim input/output (i/o) pin names are t[1,2]ch01 (timer channel 01), where ? 1 ? is used to indicate tim1 and ? 2 ? is used to indicate tim2. the two tims share two i/o pins with two i/o port pins. the full names of the tim i/o pins are listed in table 10-1 . the generic pin names appear in the text that follows. note: references to either timer 1 or timer 2 may be made in the following text by omitting the timer number. for example, tch01 may refer generically to t1ch01 and t2ch01. 10.5 functional description figure 10-1 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides the timing reference for the input capture and output compare functions. the tim counter modulo registers, tmodh:tmodl, control the modulo value of the tim counter. software can read the tim counter value at any time without affecting the counting sequence. channel 0 and channel 1 i/os are connected together, forming a common i/o. although the two tim channels are programmable independently as input capture channels, the input capture signal will be the same for both channels. output compare functions should only be enabled for one channel to avoid i/o contention. table 10-1. pin name conventions tim generic pin names: t[1,2]ch01 tclk full tim pin names: tim1 pte1/t1ch01 pte0/tclk tim2 pte2/t2ch01 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data MC68HC908JB16 ? rev. 1.0 140 timer interface module (tim) motorola figure 10-1. tim block diagram figure 10-2 summarizes the timer registers. note: references to either timer 1 or timer 2 may be made in the following text by omitting the timer number. for example, tsc may generically refer to both t1sc and t2sc. prescaler prescaler select internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus bus clock t[1,2]ch01 interrupt logic port logic interrupt logic interrupt logic port logic tclk ch01ie els0b els0a ms0a els0b els0a ms0a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola timer interface module (tim) 141 addr.register name bit 7654321bit 0 $000a timer 1 status and control register (t1sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $000c timer 1 counter register high (t1cnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $000d timer 1 counter register low (t1cntl) read: bit 7 654321bit 0 write: reset:00000000 $000e timer 1 counter modulo register high (t1modh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $000f timer 1 counter modulo register low (t1modl) read: bit 7654321bit 0 write: reset:11111111 $0010 timer 1 channel 0 status and control register (t1sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0011 timer 1 channel 0 register high (t1ch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0012 timer 1 channel 0 register low (t1ch0l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0013 timer 1 channel 1 status and control register (t1sc1) read: ch1f ch1ie ch01ie ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 10-2. tim i/o register summary (sheet 1 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data MC68HC908JB16 ? rev. 1.0 142 timer interface module (tim) motorola $0014 timer 1 channel 1 register high (t1ch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0015 timer 1 channel 1 register low (t1ch1l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0040 timer 2 status and control register (t2sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0042 timer 2 counter register high (t2cnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0043 timer 2 counter register low (t2cntl) read: bit 7 654321bit 0 write: reset:00000000 $0044 timer 2 counter modulo register high (t2modh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0045 timer 2 counter modulo register low (t2modl) read: bit 7654321bit 0 write: reset:11111111 $0046 timer 2 channel 0 status and control register (t2sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0047 timer 2 channel 0 register high (t2ch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented figure 10-2. tim i/o register summary (sheet 2 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola timer interface module (tim) 143 10.5.1 tim counter prescaler the tim clock source can be one of the seven prescaler outputs or the tim clock pin, pte0/tclk. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tim status and control register (tsc) select the tim clock source. 10.5.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the tim latches the contents of the tim counter into the tim channel registers, tchxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. $0048 timer 2 channel 0 register low (t2ch0l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0049 timer 2 channel 1 status and control register (t2sc1) read: ch1f ch1ie ch01ie ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $004a timer 2 channel 1 register high (t2ch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $004b timer 2 channel 1 register low (t2ch1l) read: bit 7654321bit 0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented figure 10-2. tim i/o register summary (sheet 3 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data MC68HC908JB16 ? rev. 1.0 144 timer interface module (tim) motorola 10.5.3 output compare with the output compare function, the tim can generate a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. 10.5.3.1 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 10.5.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchronize unbuffered changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola timer interface module (tim) 145 10.5.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the output compare value in the tim channel 0 registers initially controls the output on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the output after the tim overflows. at each subsequent overflow, the tim channel registers (0 or 1) that control the output are the ones written to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note: in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 10.5.4 pulse width modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the tim counter modulo registers. the time between overflows is the period of the pwm signal. as figure 10-3 shows, the output compare value in the tim channel registers determines the pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on output compare if the state of the pwm pulse is logic 1. program the tim to set the pin if the state of the pwm pulse is logic 0. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data MC68HC908JB16 ? rev. 1.0 146 timer interface module (tim) motorola the value in the tim counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000. see 10.10.1 tim status and control register . figure 10-3. pwm period and pulse width the value in the tim channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim channel registers produces a duty cycle of 128/256 or 50%. 10.5.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 10.5.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tim overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tim may pass the new value before it is written. tchx period pulse width overflow overflow overflow output compare output compare output compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola timer interface module (tim) 147 use the following methods to synchronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 10.5.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse width are the ones written to last. tsc0 controls and monitors the buffered pwm function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data MC68HC908JB16 ? rev. 1.0 148 timer interface module (tim) motorola note: in buffered pwm signal generation, do not write new pulse width values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 10.5.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by setting the tim stop bit, tstop. b. reset the tim counter and prescaler by setting the tim reset bit, trst. 2. in the tim counter modulo registers (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (tchxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb:msxa. (see table 10-3 .) b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 10-3 .) note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control register (tsc), clear the tim stop bit, tstop. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) interrupts MC68HC908JB16 ? rev. 1.0 technical data motorola timer interface module (tim) 149 setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim channel 0 registers (tch0h:tch0l) initially control the buffered pwm output. tim status control register 0 (tscr0) controls and monitors the pwm signal from the linked channels. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. (see 10.10.4 tim channel status and control registers .) 10.6 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? the tof bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim status and control register. tim channel flags (ch1f:ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interrupt requests are controlled by the channel x interrupt enable bit, chxie. channel x tim cpu interrupt requests are enabled when chxie = 1. chxf and chxie are in the tim channel x status and control register. 10.7 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data MC68HC908JB16 ? rev. 1.0 150 timer interface module (tim) motorola 10.7.1 wait mode the tim remains active after the execution of a wait instruction. in wait mode, the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim before executing the wait instruction. 10.7.2 stop mode the tim is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. 10.8 tim during break interrupts a break interrupt stops the tim counter. the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. (see 8.8.3 sim break flag control register (sbfcr) .) to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o signals MC68HC908JB16 ? rev. 1.0 technical data motorola timer interface module (tim) 151 10.9 i/o signals port e shares three of its pins with the tim. pte0/tclk is an external clock input to the tim prescaler. the two tim channel i/o pins are pte1/t1ch01 and pte2/t2ch01. 10.9.1 tim clock pin (pte0/tclk) pte0/tclk is an external clock input that can be the clock source for the tim counter instead of the prescaled internal bus clock. select the pte0/tclk input by writing logic 1s to the three prescaler select bits, ps[2:0]. (see 10.10.1 tim status and control register .) the minimum tclk pulse width, tclk lmin or tclk hmin , is: the maximum tclk frequency is: bus frequency f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data MC68HC908JB16 ? rev. 1.0 152 timer interface module (tim) motorola 10.10 i/o registers note: references to either timer 1 or timer 2 may be made in the following text by omitting the timer number. for example, tsc may generically refer to both t1sc and t2sc. these i/o registers control and monitor operation of the tim: tim status and control register (tsc) tim counter registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and control registers (tsc0, tsc1) tim channel registers (tch0h:tch0l, tch1h:tch1l) 10.10.1 tim status and control register the tim status and control register (tsc): enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock address: t1sc, $000a and t2sc, $0040 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 10-4. tim status and control register (tsc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola timer interface module (tim) 153 tof ? tim overflow flag bit this read/write flag is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and then writing a logic 0 to tof. if another tim overflow occurs before the clearing sequence is complete, then writing logic 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a logic 1 to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bit enables tim overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled tstop ? tim stop bit this read/write bit stops the tim counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before entering wait mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tim counter is reset and always reads as logic 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data MC68HC908JB16 ? rev. 1.0 154 timer interface module (tim) motorola ps[2:0] ? prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the tim counter as table 10-2 shows. reset clears the ps[2:0] bits. 10.10.2 tim counter registers the two read-only tim counter registers contain the high and low bytes of the value in the tim counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note: if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latched during the break. table 10-2. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock address: t1cnth, $000c and t2cnth, $0042 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 = unimplemented figure 10-5. tim counter registers high (tcnth) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola timer interface module (tim) 155 10.10.3 tim counter modulo registers the read/write tim modulo registers contain the modulo value for the tim counter. when the tim counter reaches the modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim counter modulo registers. note: reset the tim counter before writing to the tim counter modulo registers. address: t1cntl, $000d and t2cntl, $0043 bit 7654321bit 0 read: bit 7 654321bit 0 write: reset:00000000 = unimplemented figure 10-6. tim counter registers low (tcntl) address: t1modh, $000e and t2modh, $0044 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 figure 10-7. tim counter modulo register high (tmodh) address: t1modl, $000f and t2modl, $0045 bit 7654321bit 0 read: bit 7654321bit 0 write: reset:11111111 figure 10-8. tim counter modulo register low (tmodl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data MC68HC908JB16 ? rev. 1.0 156 timer interface module (tim) motorola 10.10.4 tim channel status and control registers each of the tim channel status and control registers: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on tim overflow selects 0% and 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tim counter registers matches the value in the tim channel x registers. address: t1sc0, $0010 and t2sc0, $0046 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 figure 10-9. tim channel 0 status and control register (tsc0) address: t1sc1, $0013 and t2sc1, $0049 bit 7654321bit 0 read: ch1f ch1ie ch01ie ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 figure 10-10. tim channel 1 status and control register (tsc1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola timer interface module (tim) 157 when tim cpu interrupt requests are enabled (chxie = 1), clear chxf by reading tim channel x status and control register with chxf set and then writing a logic 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables tim cpu interrupt service requests on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled ch01ie ? ch0f and ch1f interrupt enable bit this read/write bit enables tim cpu interrupt service requests when ch0f and ch1f are set. reset clears the ch01ie bit. 1 = cpu interrupt requests when ch0f and ch1f are set 0 = no cpu interrupt requests when ch0f and ch1f are set ms0b ? mode select bit b this read/write bit selects buffered output compare/pwm operation. ms0b exists only in the tim1 channel 0 and tim2 channel 0 status and control registers. setting ms0b disables the channel 1 status and control register. reset clears the ms0b bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:elsxa table 10-3 . 1 = unbuffered output compare/pwm operation 0 = input capture operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data MC68HC908JB16 ? rev. 1.0 158 timer interface module (tim) motorola when elsxb:elsxa = 0:0, this read/write bit selects the initial output level of the tchx pin. see table 10-3 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tim status and control register. elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to an i/o port, and pin tchx is available as a general-purpose i/o pin. table 10-3 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. table 10-3. mode, edge, and level selection ms0b:msxa elsxb:elsxa mode configuration x0 00 output preset pin under port control; initial output level high x1 00 pin under port control; initial output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 01 output compare or pwm (1) notes : 1. enable only one channel for unbuffered output compare or pwm functions. avoid the following configuration: ms0b = 0, ms0a = 1, ms1a = 1, and elsxb:a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola timer interface module (tim) 159 note: before enabling a tim channel register for input capture operation, make sure that the tchx pin is stable for at least two bus clocks. tovx ? toggle on overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tim counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim counter overflow 0 = channel x pin does not toggle on tim counter overflow note: when tovx is set, a tim counter overflow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at logic 1, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 10-11 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 10-11. chxmax latency 10.10.5 tim channel registers these read/write registers contain the captured tim counter value of the input capture function or the output compare value of the output compare function. the state of the tim channel registers after reset is unknown. output overflow tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data MC68HC908JB16 ? rev. 1.0 160 timer interface module (tim) motorola in input capture mode (msxb:msxa = 0:0), reading the high byte of the tim channel x registers (tchxh) inhibits input captures until the low byte (tchxl) is read. in output compare mode (msxb:msxa address: t1ch0h, $0011 and t2ch0h, $0047 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 10-12. tim channel 0 register high (tch0h) address: t1ch0l, $0012 and t2ch0l $0048 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 10-13. tim channel 0 register low (tch0l) address: t1ch1h, $0014 and t2ch1h, $004a bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 10-14. tim channel 1 register high (tch1h) address: t1ch1l, $0015 and t2ch1l, $004b bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 10-15. tim channel 1 register low (tch1l) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 161 technical data ? MC68HC908JB16 section 11. universal serial bus module (usb) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.5.1 usb protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.5.1.1 sync pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 11.5.1.2 packet identifier field . . . . . . . . . . . . . . . . . . . . . . . . . .171 11.5.1.3 address field (addr) . . . . . . . . . . . . . . . . . . . . . . . . . .172 11.5.1.4 endpoint field (endp). . . . . . . . . . . . . . . . . . . . . . . . . .172 11.5.1.5 cyclic redundancy check (crc) . . . . . . . . . . . . . . . . . 172 11.5.1.6 end-of-packet (eop) . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 11.5.2 reset signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 11.5.3 suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.5.4 resume after suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.5.4.1 host initiated resume . . . . . . . . . . . . . . . . . . . . . . . . . .175 11.5.4.2 usb reset signalling. . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.5.4.3 remote wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.5.5 low-speed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 11.6 clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 11.7 hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.1 voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.2 usb transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.2.1 output driver characteristics . . . . . . . . . . . . . . . . . . . . . 178 11.7.2.2 low speed (1.5 mbps) driver characteristics . . . . . . . . 178 11.7.2.3 receiver data jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11.7.2.4 data source jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11.7.2.5 data signal rise and fall time . . . . . . . . . . . . . . . . . . .180 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 162 universal serial bus module (usb) motorola 11.7.3 usb control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.8.1 usb address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.8.2 usb interrupt register 0 . . . . . . . . . . . . . . . . . . . . . . . . . .183 11.8.3 usb interrupt register 1 . . . . . . . . . . . . . . . . . . . . . . . . . .185 11.8.4 usb interrupt register 2 . . . . . . . . . . . . . . . . . . . . . . . . . .188 11.8.5 usb control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 11.8.6 usb control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 11.8.7 usb control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11.8.8 usb control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 11.8.9 usb control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.8.10 usb status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 11.8.11 usb status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 11.8.12 usb endpoint 0 data registers . . . . . . . . . . . . . . . . . . . . . 198 11.8.13 usb endpoint 1 data registers . . . . . . . . . . . . . . . . . . . . . 199 11.8.14 usb endpoint 2 data registers . . . . . . . . . . . . . . . . . . . . . 200 11.9 usb interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 11.9.1 usb end-of-transaction interrupt . . . . . . . . . . . . . . . . . . .201 11.9.1.1 receive control endpoint 0 . . . . . . . . . . . . . . . . . . . . . .202 11.9.1.2 transmit control endpoint 0 . . . . . . . . . . . . . . . . . . . . .204 11.9.1.3 transmit endpoint 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 11.9.1.4 transmit endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 11.9.1.5 receive endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 11.9.2 resume interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 11.9.3 end-of-packet interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 11.2 introduction this section describes the universal serial bus (usb) module. the usb module is designed to serve as a low-speed (ls) usb device per the universal serial bus specification rev. 2.0 . control and interrupt data transfers are supported. endpoint 0 functions as a transmit/receive control endpoint; endpoint 1 functions as interrupt transmit endpoint; endpoint 2 functions as interrupt transmit or receive endpoint. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) features MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 163 11.3 features features of the usb module include: universal serial bus specification 2.0 low-speed functions 1.5 mbps data rate on-chip 3.3v regulator endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer endpoint 1 with 8-byte transmit buffer endpoint 2 with 8-byte transmit buffer and 8-byte receive buffer usb data control logic: ? control endpoint 0 and interrupt endpoints 1 and 2 ? packet decoding/generation ? crc generation and checking ? nrzi (non-return-to zero inserted) encoding/decoding ? bit-stuffing usb reset options: ? internal mcu reset generation ? cpu interrupt request generation suspend and resume operations, with remote wakeup support usb-generated interrupts: ? transaction interrupt driven ? resume interrupt ? end-of-packet interrupt ? usb reset stall, nak, and ack handshake generation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 164 universal serial bus module (usb) motorola 11.4 pin name conventions the usb share two i/o pins with two port e i/o pins. the full name of the usb i/o pin is listed in table 11-1 . the generic pin name appear in the text that follows. table 11-1. usb module pin name conventions usb generic pin names: d+ d? full usb pin names: pte3/d+ pte4/d ? addr.register name bit 7654321bit 0 $0018 usb interrupt register 2 (uir2) read: 00000000 write: eopfr rstfr txd2fr rxd2fr txd1fr resumfr txd0fr rxd0fr reset:00000000 $0019 usb control register 2 (ucr2) read: t2seq stall2 tx2e rx2e tp2siz3 tp2siz2 tp2siz1 tp2siz0 write: reset:00000000 $001a usb control register 3 (ucr3) read: tx1st 0 ostall0 istall0 0 pullen enable2 enable1 write: tx1str reset:000000*00 * pullen bit is reset by por or lvi reset only. $001b usb control register 4 (ucr4) read: 00000 fusbo fdp fdm write: reset:00000000 $0020 usb endpoint 0 data register 0 (ue0d0) read: ue0r07 ue0r06 ue0r05 ue0r04 ue0r03 ue0r02 ue0r01 ue0r00 write: ue0t07 ue0t06 ue0t05 ue0t04 ue0t03 ue0t02 ue0t01 ue0t00 reset: unaffected by reset $0021 usb endpoint 0 data register 1 (ue0d1) read: ue0r17 ue0r16 ue0r15 ue0r14 ue0r13 ue0r12 ue0r11 ue0r10 write: ue0t17 ue0t16 ue0t15 ue0t14 ue0t13 ue0t12 ue0t11 ue0t10 reset: unaffected by reset = unimplemented u = unaffected by reset figure 11-1. usb i/o register summary (sheet 1 of 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) pin name conventions MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 165 $0022 usb endpoint 0 data register 2 (ue0d2) read: ue0r27 ue0r26 ue0r25 ue0r24 ue0r23 ue0r22 ue0r21 ue0r20 write: ue0t27 ue0t26 ue0t25 ue0t24 ue0t23 ue0t22 ue0t21 ue0t20 reset: unaffected by reset $0023 usb endpoint 0 data register 3 (ue0d3) read: ue0r37 ue0r36 ue0r35 ue0r34 ue0r33 ue0r32 ue0r31 ue0r30 write: ue0t37 ue0t36 ue0t35 ue0t34 ue0t33 ue0t32 ue0t31 ue0t30 reset: unaffected by reset $0024 usb endpoint 0 data register 4 (ue0d4) read: ue0r47 ue0r46 ue0r45 ue0r44 ue0r43 ue0r42 ue0r41 ue0r40 write: ue0t47 ue0t46 ue0t45 ue0t44 ue0t43 ue0t42 ue0t41 ue0t40 reset: unaffected by reset $0025 usb endpoint 0 data register 5 (ue0d5) read: ue0r57 ue0r56 ue0r55 ue0r54 ue0r53 ue0r52 ue0r51 ue0r50 write: ue0t57 ue0t56 ue0t55 ue0t54 ue0t53 ue0t52 ue0t51 ue0t50 reset: unaffected by reset $0026 usb endpoint 0 data register 6 (ue0d6) read: ue0r67 ue0r66 ue0r65 ue0r64 ue0r63 ue0r62 ue0r61 ue0r60 write: ue0t67 ue0t66 ue0t65 ue0t64 ue0t63 ue0t62 ue0t61 ue0t60 reset: unaffected by reset $0027 usb endpoint 0 data register 7 (ue0d7) read: ue0r77 ue0r76 ue0r75 ue0r74 ue0r73 ue0r72 ue0r71 ue0r70 write: ue0t77 ue0t76 ue0t75 ue0t74 ue0t73 ue0t72 ue0t71 ue0t70 reset: unaffected by reset $0028 usb endpoint 1 data register 0 (ue1d0) read: write: ue1t07 ue1t06 ue1t05 ue1t04 ue1t03 ue1t02 ue1t01 ue1t00 reset: unaffected by reset $0029 usb endpoint 1 data register 1 (ue1d1) read: write: ue1t17 ue1t16 ue1t15 ue1t14 ue1t13 ue1t12 ue1t11 ue1t10 reset: unaffected by reset $002a usb endpoint 1 data register 2 (ue1d2) read: write: ue1t27 ue1t26 ue1t25 ue1t24 ue1t23 ue1t22 ue1t21 ue1t20 reset: unaffected by reset $002b usb endpoint 1 data register 3 (ue1d3) read: write: ue1t37 ue1t36 ue1t35 ue1t34 ue1t33 ue1t32 ue1t31 ue1t30 reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented u = unaffected by reset figure 11-1. usb i/o register summary (sheet 2 of 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 166 universal serial bus module (usb) motorola $002c usb endpoint 1 data register 4 (ue1d4) read: write: ue1t47 ue1t46 ue1t45 ue1t44 ue1t43 ue1t42 ue1t41 ue1t40 reset: unaffected by reset $002d usb endpoint 1 data register5 (ue1d5) read: write: ue1t57 ue1t56 ue1t55 ue1t54 ue1t53 ue1t52 ue1t51 ue1t50 reset: unaffected by reset $002e usb endpoint 1 data register 6 (ue1d6) read: write: ue1t67 ue1t66 ue1t65 ue1t64 ue1t63 ue1t62 ue1t61 ue1t60 reset: unaffected by reset $002f usb endpoint 1 data register 7 (ue1d7) read: write: ue1t77 ue1t76 ue1t75 ue1t74 ue1t73 ue1t72 ue1t71 ue1t70 reset: unaffected by reset $0030 usb endpoint 2 data register 0 (ue2d0) read: ue2r07 ue2r06 ue2r05 ue2r04 ue2r03 ue2r02 ue2r01 ue2r00 write: ue2t07 ue2t06 ue2t05 ue2t04 ue2t03 ue2t02 ue2t01 ue2t00 reset: unaffected by reset $0031 usb endpoint 2 data register 1 (ue2d1) read: ue2r17 ue2r16 ue2r15 ue2r14 ue2r13 ue2r12 ue2r11 ue2r10 write: ue2t17 ue2t16 ue2t15 ue2t14 ue2t13 ue2t12 ue2t11 ue2t10 reset: unaffected by reset $0032 usb endpoint 2 data register 2 (ue2d2) read: ue2r27 ue2r26 ue2r25 ue2r24 ue2r23 ue2r22 ue2r21 ue2r20 write: ue2t27 ue2t26 ue2t25 ue2t24 ue2t23 ue2t22 ue2t21 ue2t20 reset: unaffected by reset $0033 usb endpoint 2 data register 3 (ue2d3) read: ue2r37 ue2r36 ue2r35 ue2r34 ue2r33 ue2r32 ue2r31 ue2r30 write: ue2t37 ue2t36 ue2t35 ue2t34 ue2t33 ue2t32 ue2t31 ue2t30 reset: unaffected by reset $0034 usb endpoint 2 data register 4 (ue2d4) read: ue2r47 ue2r46 ue2r45 ue2r44 ue2r43 ue2r42 ue2r41 ue2r40 write: ue2t47 ue2t46 ue2t45 ue2t44 ue2t43 ue2t42 ue2t41 ue2t40 reset: unaffected by reset $0035 usb endpoint 2 data register 5 (ue2d5) read: ue2r57 ue2r56 ue2r55 ue2r54 ue2r53 ue2r52 ue2r51 ue2r50 write: ue2t57 ue2t56 ue2t55 ue2t54 ue2t53 ue2t52 ue2t51 ue2t50 reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented u = unaffected by reset figure 11-1. usb i/o register summary (sheet 3 of 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) pin name conventions MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 167 $0036 usb endpoint 2 data register 6 (ue2d6) read: ue2r67 ue2r66 ue2r65 ue2r64 ue2r63 ue2r62 ue2r61 ue2r60 write: ue2t67 ue2t66 ue2t65 ue2t64 ue2t63 ue2t62 ue2t61 ue2t60 reset: unaffected by reset $0037 usb endpoint 2 data register 7 (ue2d7) read: ue2r77 ue2r76 ue2r75 ue2r74 ue2r73 ue2r72 ue2r71 ue2r70 write: ue2t77 ue2t76 ue2t75 ue2t74 ue2t73 ue2t72 ue2t71 ue2t70 reset: unaffected by reset $0038 usb address register (uaddr) read: usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 write: reset:0*0000000 * usben bit is reset by por or lvi reset only. $0039 usb interrupt register 0 (uir0) read: eopie suspnd txd2ie rxd2ie txd1ie 0 txd0ie rxd0ie write: reset:00000000 $003a usb interrupt register 1 (uir1) read: eopf rstf txd2f rxd2f txd1f resumf txd0f rxd0f write: reset:00000000 $003b usb control register 0 (ucr0) read: t0seq 0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset:00000000 $003c usb control register 1 (ucr1) read: t1seq stall1 tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset:00000000 $003d usb status register 0 (usr0) read: r0seq setup 0 0 rp0siz3 rp0siz2 rp0siz1 rp0siz0 write: reset: unaffected by reset $003e usb status register 1 (usr1) read: r2seq txack txnak txstl rp2siz3 rp2siz2 rp2siz1 rp2siz0 write: reset:u0 0 0uuuu addr.register name bit 7654321bit 0 = unimplemented u = unaffected by reset figure 11-1. usb i/o register summary (sheet 4 of 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 168 universal serial bus module (usb) motorola 11.5 functional description figure 11-2 shows the block diagram of the usb module. the usb module manages communications between the host and the usb function. the module is partitioned into three functional blocks. these blocks consist of a dual-function transceiver, the usb control logic, and the endpoint registers. the blocks are further detailed later in this section (see 11.7 hardware description ). figure 11-2. usb block diagram d + d ? transceiver rcv vpin vmin vpout vmout cpu bus usb registers usb upstream port usb control logic 6mhz from osc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 169 11.5.1 usb protocol figure 11-3 shows the various transaction types supported by the usb module. the transactions are portrayed as error free. the effect of errors in the data flow are discussed later. figure 11-3. supported transaction types per endpoint setup in out data0/1 data0 data1 ack data1 out ack out data0 ack ack data0/1 endpoint 0 transactions: control write control read no-data control endpoints 1 & 2 transactions: interrupt bulk transmit in ack key: unrelated bus traffic host generated device generated ack setup out in data0/1 data0 data1 ack data1 in ack in data0 ack ack ack setup in data0 data1 ack ack data0/1 in ack f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 170 universal serial bus module (usb) motorola each usb transaction is comprised of a series of packets. the usb module supports the packet types shown in figure 11-4 . token packets are generated by the usb host and decoded by the usb device. data and handshake packets are both decoded and generated by the usb device, depending on the type of transaction. figure 11-4. supported usb packet types the following sections detail each segment used to form a complete usb transaction. 11.5.1.1 sync pattern the nrzi bit pattern shown in figure 11-5 is used as a synchronization pattern and is prefixed to each packet. this pattern is equivalent to a data pattern of seven 0s followed by a 1 ($80). figure 11-5. sync pattern token packet: in out sync pid pid addr endp crc5 eop setup data packet: data0 sync pid pid data crc16 eop data1 0 ? 8 bytes handshake packet: ack nak sync pid pid eop stall sync pattern pid0 pid1 idle nrzi data encoding f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 171 the start of a packet (sop) is signaled by the originating port by driving the d+ and d ? lines from the idle state (also referred to as the j state) to the opposite logic level (also referred to as the k state). this switch in levels represents the first bit of the sync field. figure 11-6 shows the data signaling and voltage levels for the start of packet and the sync pattern. figure 11-6. sop, sync signaling, and voltage levels 11.5.1.2 packet identifier field the packet identifier field is an 8-bit number comprised of the 4-bit packet identification and its complement. the field follows the sync pattern and determines the direction and type of transaction on the bus. table 11-2 shows the packet identifier values for the supported packet types. end of sync first bit of packet sop bus idle v oh (min.) v se (max) v se (min.) v ol (min.) v ss table 11-2. supported packet identifiers packet identifier value packet identifier type %1001 in token %0001 out token %1101 setup token %0011 data0 packet %1011 data1 packet %0010 ack handshake %1010 nak handshake %1110 stall handshake f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 172 universal serial bus module (usb) motorola 11.5.1.3 address field (addr) the address field is a 7-bit number that is used to select a particular usb device. this field is compared to the lower seven bits of the uaddr register to determine if a given transaction is targeting the mcu usb device. 11.5.1.4 endpoint field (endp) the endpoint field is a 4-bit number that is used to select a particular endpoint within a usb device. for the mcu, this will be a binary number between 0 and 2 inclusive. any other value will cause the transaction to be ignored. 11.5.1.5 cyclic redundancy check (crc) cyclic redundancy checks are used to verify the address and data stream of a usb transaction. this field is five bits wide for token packets and 16 bits wide for data packets. crcs are generated in the transmitter and sent on the usb data lines after both the endpoint field and the data field. 11.5.1.6 end-of-packet (eop) the single-ended 0 (se0) state is used to signal an end-of-packet (eop). the single-ended 0 state is indicated by both d+ and d ? being below 0.8v. eop will be signaled by driving d+ and d ? to the single- ended 0 state for two bit times followed by driving the lines to the idle state for one bit time. the transition from the single-ended 0 to the idle state defines the end of the packet. the idle state is asserted for one bit time and then both the d+ and d ? output drivers are placed in their high- impedance state. the bus termination resistors hold the bus in the idle state. figure 11-7 shows the data signaling and voltage levels for an end-of-packet transaction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 173 figure 11-7. eop transaction voltage levels the width of the se0 in the eop is about two bit times. the eop width is measured with the same capacitive load used for maximum rise and fall times and is measured at the same level as the differential signal crossover points of the data lines. figure 11-8. eop width timing 11.5.2 reset signaling the usb module will detect a reset signaled on the bus by the presence of an extended se0 at the usb data pins of a device. the mcu seeing a single-ended 0 on its usb data inputs for more than 8 8.8.2 sim reset status register (srsr) for more detail. the mcu ? s reset recovery sequence is detailed in section 8. system integration module (sim) . bus driven to last bit of bus idle eop strobe packet idle state bus floats v oh (min.) v se (max) v se (min.) v ol (min.) v ss eop width t period differential data lines data crossover level f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 174 universal serial bus module (usb) motorola the reset flag bit (rstf) in the usb interrupt register 1 (uir1) also will be set after the internal reset is removed. refer to 11.8.3 usb interrupt register 1 for more detail. after a reset is removed, the device will be in the default, but not yet addressed or configured state (refer to section 9.1 usb device states of the universal serial bus specification rev. 2.0 ). the device must be able to accept a device address via a set_address command (refer to section 9.4 standard device request in the universal serial bus specification rev. 2.0 ) no later than 10ms after the reset is removed. reset can wake a device from the suspended mode. note: usb reset can be configured not to generate a reset signal to the cpu by setting the urstd bit of the configuration register (see section 5. configuration register (config) ). when a usb reset is detected, the cpu generates an usb interrupt. 11.5.3 suspend the mcu supports suspend mode for low power. suspend mode should be entered when the usb data lines are in the idle state for more than 3ms. entry into suspend mode is controlled by the suspnd bit in the usb interrupt register. any low-speed bus activity should keep the device out of the suspend state. low-speed devices are kept awake by periodic low-speed eop signals from the host. this is referred to as low speed keep alive (refer to section 11.8.4.1 low-speed keep-alive in the universal serial bus specification rev. 2.0 ). firmware should monitor the eopf flag and enter suspend mode by setting the suspnd bit if an eop is not detected for 3ms. per the usb specification, the bus powered usb system is required to draw less than 500 ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 175 11.5.4 resume after suspend the mcu can be activated from the suspend state by normal bus activity, a usb reset signal, or by a forced resume driven from the mcu. 11.5.4.1 host initiated resume the host signals resume by initiating resume signalling (k state) for at least 20ms followed by a standard low-speed eop signal. this 20ms ensures that all devices in the usb network are awakened. after resuming the bus, the host must begin sending bus traffic within 3ms to prevent the device from re-entering suspend mode. 11.5.4.2 usb reset signalling reset can wake a device from the suspended mode. 11.5.4.3 remote wakeup the mcu also supports the remote wakeup feature. the firmware has the ability to exit suspend mode by signaling a resume state to the upstream host or hub. a non-idle state (k state) on the usb data lines is accomplished by asserting the fresum bit in the ucr1 register. when using the remote wakeup capability, the firmware must wait for at least 5ms after the bus is in the idle state before sending the remote wakeup resume signaling. this allows the upstream devices to get into their suspend state and prepare for propagating resume signaling. the fresum bit should be asserted to cause the resume state on the usb data lines for at least 10ms, but not more than 15ms. note that the resume signalling is controlled by the fresum bit and meeting the timing specifications is dependent on the firmware. when fresum is cleared by firmware, the data lines will return to their high-impedance state. refer to register definitions (see 11.8.6 usb control register 1 ) for more information about how the force resume (fresum) bit can be used to initiate the remote wakeup feature. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 176 universal serial bus module (usb) motorola 11.5.5 low-speed device low-speed devices are configured by the position of a pull-up resistor on the usb d ? pin of the mcu. low-speed devices are terminated as shown in figure 11-9 with the pull-up on the d ? line. figure 11-9. external low-speed device configuration for low-speed transmissions, the transmitter ? s eop width must be between 1.25 1.5 k ? d+ d ? v reg (3.3v) usb low-speed cable mcu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) hardware description MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 177 11.7 hardware description the usb module as previously shown in figure 11-2 contains three functional blocks: the low-speed usb transceiver, the usb control logic, and the usb registers. the following details the function of the regulator, transceiver, and control logic. see 11.8 i/o registers for details of register settings. 11.7.1 voltage regulator the usb data lines are required by the usb specification to have an output voltage between 2.8v and 3.6v. the data lines also are required to have an external 1.5k ? figure 11-10 shows the worst case electrical connection for the voltage regulator. figure 11-10. regulator electrical connections 11.7.2 usb transceiver the usb transceiver provides the physical interface to the usb d+ and d ? data lines. the transceiver is composed of two parts: an output drive circuit and a receiver. r1 d+ d ? usb cable low-speed transceiver r2 r2 host or hub 3.3v regulator 4.0v to 5.5v usb data lines r1 = 1.5k ? 5% r2 = 15k ? 5% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 178 universal serial bus module (usb) motorola 11.7.2.1 output driver characteristics the usb transceiver uses a differential output driver to drive the usb data signal onto the usb cable. the static output swing of the driver in its low state is below the v ol of 0.3v with a 1.5k ? ? ? s outputs support 3-state operation to achieve bidirectional half duplex operation. the driver can tolerate a voltage on the signal pins of ? 1.0v to 5.5v with respect to local ground reference without damage. 11.7.2.2 low speed (1.5 mbps) driver characteristics the rise and fall time of the signals on this cable are greater than 75ns and less than 300ns. the edges are matched to within ? as seen at the receiver, and a differential 0 is represented by d ? being at least 200mv more positive than d+ as seen at the receiver. the signal cross over point must be between 1.3v and 2.0v. figure 11-11. receiver characteristics one bit time (1.5 mb/s) signal pins pass output spec levels with minimal reflections and ringing v se (min.) v se (max) v ss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) hardware description MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 179 the receiver features an input sensitivity of 200mv when both differential data inputs are in the differential common mode range of 0.8v to 2.5v as shown in figure 11-12 . in addition to the differential receiver, there is a single-ended receiver (schmitt trigger) for each of the two data lines. figure 11-12. differential input sensitivity range 11.7.2.3 receiver data jitter the data receivers for all types of devices must be able to properly decode the differential data in the presence of jitter. the more of the bit time that any data edge can occupy and still be decoded, the more reliable the data transfer will be. data receivers are required to decode differential data transitions that occur in a window plus and minus a nominal quarter bit time from the nominal (centered) data edge position. jitter will be caused by the delay mismatches and by mismatches in the source and destination data rates (frequencies). the receive data jitter budget for low speed is given in section 20. electrical specifications . the specification includes the consecutive (next) and paired transition values for each source of jitter. 11.7.2.4 data source jitter the source of data can have some variation (jitter) in the timing of edges of the data transmitted. the time between any set of data transitions is n figure 11-13 . differential output crossover voltage range differential input voltage range input voltage range (volts) 0.00.20.40.60.81.01.21.41.61.82.02.22.42.62.83.03.2 ? 1.0 5.5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 180 universal serial bus module (usb) motorola figure 11-13. data jitter for low-speed transmissions, the jitter time for any consecutive differential data transitions must be within 11.7.2.5 data signal rise and fall time the output rise time and fall time are measured between 10% and 90% of the signal. edge transition time for the rising and falling edges of low- speed signals is 75ns (minimum) into a capacitive load (c l ) of 200pf and 300ns (maximum) into a capacitive load of 600pf. the rising and falling edges should be transitioning (monotonic) smoothly when driving the cable to avoid excessive emi. figure 11-14. data signal rise and fall time consecutive transitions t period differential data lines crossover points paired transitions jitter t r differential data lines t f rise time fall time 10% 90% 90% 10% low speed: 75ns at c l = 200pf, 300ns at c l = 600 pf c l c l + + f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 181 11.7.3 usb control logic the usb control logic manages data movement between the cpu and the transceiver. the control logic handles both transmit and receive operations on the usb. it contains the logic used to manipulate the transceiver and the endpoint registers. the byte count buffer is loaded with the active transmit endpoints byte count value during transmit operations. this same buffer is used for receive transactions to count the number of bytes received and, upon the end of the transaction, transfer that number to the receive endpoints byte count register. when transmitting, the control logic handles parallel-to-serial conversion, crc generation, nrzi encoding, and bit stuffing. when receiving, the control logic handles sync detection, packet identification, end-of-packet detection, bit (un)stuffing, nrzi decoding, crc validation, and serial-to-parallel conversion. errors detected by the control logic include bad crc, timeout while waiting for eop, and bit stuffing violations. 11.8 i/o registers these i/o registers control and monitor usb operation: usb address register (uaddr) usb control registers 0 ? 4 (ucr0 ? ucr4) usb status registers 0 ? 1 (usr0 ? usr1) usb interrupt registers 0 ? 2 (uir0 ? uir2) usb endpoint 0 data registers 0 ? 7 (ue0d0 ? ue0d7) usb endpoint 1 data registers 0 ? 7 (ue1d0 ? ue1d7) usb endpoint 2 data registers 0 ? 7 (ue2d0 ? ue2d7) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 182 universal serial bus module (usb) motorola 11.8.1 usb address register usben ? usb module enable this read/write bit enables and disables the usb module and the usb pins. when usben is set, the usb module is enabled and the pte4 interrupt is disabled. when usben is clear, the usb module will not respond to any tokens, usb reset and usb related interrupts are disabled, and pins pte4/d ? and pte3/d+ function as high current open-drain i/o port pins pte4 and pte3. 1 = usb function enabled and pte4 interrupt is disabled 0 = usb function disabled including usb interrupt, reset and reset interrupt uadd[6:0] ? usb function address these bits specify the usb address of the device. reset clears these bits. address: $0038 bit 7654321bit 0 read: usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 write: reset: 0*0000000 * usben bit is reset by por or lvi reset only. figure 11-15. usb address register (uaddr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 183 11.8.2 usb interrupt register 0 eopie ? end-of-packet detect interrupt enable this read/write bit enables the usb to generate cpu interrupt requests when the eopf bit becomes set. reset clears the eopie bit. 1 = end-of-packet sequence detection can generate a cpu interrupt request 0 = end-of-packet sequence detection cannot generate a cpu interrupt request suspnd ? usb suspend bit to save power, this read/write bit should be set by the software if a 3ms constant idle state is detected on the usb bus. setting this bit puts the transceiver into a power-saving mode. the resumf flag must be cleared before setting suspnd. software must clear this bit after the resume flag (resumf) is set while this resume interrupt flag is serviced. txd2ie ? endpoint 2 transmit interrupt enable this read/write bit enables the transmit endpoint 2 to generate cpu interrupt requests when the txd2f bit becomes set. reset clears the txd2ie bit. 1 = transmit endpoint 2 can generate a cpu interrupt request 0 = transmit endpoint 2 cannot generate a cpu interrupt request address: $0039 bit 7654321bit 0 read: eopie suspnd txd2ie rxd2ie txd1ie 0 txd0ie rxd0ie write: reset:00000000 = unimplemented figure 11-16. usb interrupt register 0 (uir0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 184 universal serial bus module (usb) motorola rxd2ie ? endpoint 2 receive interrupt enable this read/write bit enables the receive endpoint 2 to generate cpu interrupt requests when the rxd2f bit becomes set. reset clears the rxd2ie bit. 1 = receive endpoint 2 can generate a cpu interrupt request 0 = receive endpoint 2 cannot generate a cpu interrupt request txd1ie ? endpoint 1 transmit interrupt enable this read/write bit enables the transmit endpoint 1 to generate cpu interrupt requests when the txd1f bit becomes set. reset clears the txd1ie bit. 1 = transmit endpoints 1 can generate a cpu interrupt request 0 = transmit endpoints 1 cannot generate a cpu interrupt request txd0ie ? endpoint 0 transmit interrupt enable this read/write bit enables the transmit endpoint 0 to generate cpu interrupt requests when the txd0f bit becomes set. reset clears the txd0ie bit. 1 = transmit endpoint 0 can generate a cpu interrupt request 0 = transmit endpoint 0 cannot generate a cpu interrupt request rxd0ie ? endpoint 0 receive interrupt enable this read/write bit enables the receive endpoint 0 to generate cpu interrupt requests when the rxd0f bit becomes set. reset clears the rxd0ie bit. 1 = receive endpoint 0 can generate a cpu interrupt request 0 = receive endpoint 0 cannot generate a cpu interrupt request f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 185 11.8.3 usb interrupt register 1 eopf ? end-of-packet detect flag this read-only bit is set when a valid end-of-packet sequence is detected on the d+ and d ? lines. software must clear this flag by writing a logic 1 to the eopfr bit. reset clears this bit. writing to eopf has no effect. 1 = end-of-packet sequence has been detected 0 = end-of-packet sequence has not been detected rstf ? usb reset flag this read-only bit is set when a valid reset signal state is detected on the d+ and d ? lines. if the urstd bit of the configuration register (config) is clear, this reset detection will generate an internal reset signal to reset the cpu and other peripherals including the usb module. if the urstd bit is set, this reset detection will generate an usb interrupt. this bit is cleared by writing a logic 1 to the rstfr bit. this bit also is cleared by a por reset. note: the usb bit in the srsr (see 8.8.2 sim reset status register (srsr) ) is also a usb reset indicator. txd2f ? endpoint 2 data transmit flag this read-only bit is set after the data stored in endpoint 2 transmit buffers has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the txd2fr bit. address: $003a bit 7654321bit 0 read: eopf rstf txd2f rxd2f txd1f resumf txd0f rxd0f write: reset:00000000 = unimplemented figure 11-17. usb interrupt register 1 (uir1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 186 universal serial bus module (usb) motorola to enable the next data packet transmission, tx2e also must be set. if the txd2f bit is not cleared, a nak handshake will be returned in the next in transaction. reset clears this bit. writing to txd2f has no effect. 1 = transmit on endpoint 2 has occurred 0 = transmit on endpoint 2 has not occurred rxd2f ? endpoint 2 data receive flag this read-only bit is set after the usb module has received a data packet and responded with an ack handshake packet. software must clear this flag by writing a logic 1 to the rxd2fr bit after all of the received data has been read. software also must set the rx2e bit to 1 to enable the next data packet reception. if the rxd2f bit is not cleared, a nak handshake will be returned in the next out transaction. reset clears this bit. writing to rxd2f has no effect. 1 = receive on endpoint 2 has occurred 0 = receive on endpoint 2 has not occurred txd1f ? endpoint 1 data transmit flag this read-only bit is set after the data stored in the endpoint 1 transmit buffer has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the txd1fr bit. to enable the next data packet transmission, tx1e also must be set. if the txd1f bit is not cleared, a nak handshake will be returned in the next in transaction. reset clears this bit. writing to txd1f has no effect. 1 = transmit on endpoint 1has occurred 0 = transmit on endpoint 1has not occurred resumf ? resume flag this read-only bit is set when usb bus activity is detected while the suspnd bit is set. software must clear this flag by writing a logic 1 to the resumfr bit. reset clears this bit. writing a logic 0 to resumf has no effect. 1 = usb bus activity has been detected 0 = no usb bus activity has been detected f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 187 txd0f ? endpoint 0 data transmit flag this read-only bit is set after the data stored in endpoint 0 transmit buffers has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the txd0fr bit. to enable the next data packet transmission, tx0e also must be set. if the txd0f bit is not cleared, a nak handshake will be returned in the next in transaction. reset clears this bit. writing to txd0f has no effect. 1 = transmit on endpoint 0 has occurred 0 = transmit on endpoint 0 has not occurred rxd0f ? endpoint 0 data receive flag this read-only bit is set after the usb module has received a data packet and responded with an ack handshake packet. software must clear this flag by writing a logic 1 to the rxd0fr bit after all of the received data has been read. software also must set the rx0e bit to 1 to enable the next data packet reception. if the rxd0f bit is not cleared, the usb will respond with a nak handshake to any endpoint 0 out tokens; but does not respond to a setup token. reset clears this bit. writing to rxd0f has no effect. 1 = receive on endpoint 0 has occurred 0 = receive on endpoint 0 has not occurred f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 188 universal serial bus module (usb) motorola 11.8.4 usb interrupt register 2 eopfr ? end-of-packet flag reset writing a logic 1 to this write-only bit will clear the eopf bit if it is set. writing a logic 0 to the eopfr has no effect. reset clears this bit. rstfr ? clear reset indicator bit writing a logic 1 to this write-only bit will clear the rstf bit if it is set. writing a logic 0 to the rstfr has no effect. reset clears this bit. txd2fr ? endpoint 2 transmit flag reset writing a logic 1 to this write-only bit will clear the txd2f bit if it is set. writing a logic 0 to txd2fr has no effect. reset clears this bit. rxd2fr ? endpoint 2 receive flag reset writing a logic 1 to this write-only bit will clear the rxd2f bit if it is set. writing a logic 0 to rxd2fr has no effect. reset clears this bit. txd1fr ? endpoint 1 transmit flag reset writing a logic 1 to this write-only bit will clear the txd1f bit if it is set. writing a logic 0 to txd1fr has no effect. reset clears this bit. resumfr ? resume flag reset writing a logic 1 to this write-only bit will clear the resumf bit if it is set. writing to resumfr has no effect. reset clears this bit. txd0fr ? endpoint 0 transmit flag reset writing a logic 1 to this write-only bit will clear the txd0f bit if it is set. writing a logic 0 to txd0fr has no effect. reset clears this bit. rxd0fr ? endpoint 0 receive flag reset writing a logic 1 to this write-only bit will clear the rxd0f bit if it is set. writing a logic 0 to rxd0fr has no effect. reset clears this bit. address: $0018 bit 7654321bit 0 read: 00 0 0 0 0 0 0 write: eopfr rstfr txd2fr rxd2fr txd1fr resumfr txd0fr rxd0fr reset:00000000 figure 11-18. usb interrupt register 2 (uir2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 189 11.8.5 usb control register 0 t0seq ? endpoint 0 transmit sequence bit this read/write bit determines which type of data packet (data0 or data1) will be sent during the next in transaction directed at endpoint 0. toggling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active for next endpoint 0 transmit 0 = data0 token active for next endpoint 0 transmit tx0e ? endpoint 0 transmit enable this read/write bit enables a transmit to occur when the usb host controller sends an in token to endpoint 0. software should set this bit when data is ready to be transmitted. it must be cleared by software when no more endpoint 0 data needs to be transmitted. if this bit is 0 or the txd0f is set, the usb will respond with a nak handshake to any endpoint 0 in tokens. reset clears this bit. 1 = data is ready to be sent 0 = data is not ready. respond with nak rx0e ? endpoint 0 receive enable this read/write bit enables a receive to occur when the usb host controller sends an out token to endpoint 0. software should set this bit when data is ready to be received. it must be cleared by software when data cannot be received. if this bit is 0 or the rxd0f is set, the usb will respond with a nak handshake to any endpoint 0 out tokens; but does not respond to a setup token. reset clears this bit. 1 = data is ready to be received 0 = not ready for data. respond with nak address: $003b bit 7654321bit 0 read: t0seq 0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset:00000000 figure 11-19. usb control register 0 (ucr0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 190 universal serial bus module (usb) motorola tp0siz3 ? tp0siz0 ? endpoint 0 transmit data packet size these read/write bits store the number of transmit data bytes for the next in token request for endpoint 0. these bits are cleared by reset. 11.8.6 usb control register 1 t1seq ? endpoint 1 transmit sequence bit this read/write bit determines which type of data packet (data0 or data1) will be sent during the next in transaction directed to endpoint 1. toggling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active for next endpoint 1 transmit 0 = data0 token active for next endpoint 1 transmit stall1 ? endpoint 1 force stall bit this read/write bit causes endpoint 1 to return a stall handshake when polled by either an in or out token by the usb host controller. reset clears this bit. 1 = send stall handshake 0 = default tx1e ? endpoint 1 transmit enable this read/write bit enables a transmit to occur when the usb host controller sends an in token to endpoint 1. the appropriate endpoint enable bit, enable1 bit in the ucr3 register, also should be set. software should set the tx1e bit when data is ready to be transmitted. it must be cleared by software when no more data needs to be transmitted. address: $003c bit 7654321bit 0 read: t1seq stall1 tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset:00000000 figure 11-20. usb control register 1 (ucr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 191 if this bit is 0 or the txd1f is set, the usb will respond with a nak handshake to any endpoint 1 directed in tokens. reset clears this bit. 1 = data is ready to be sent 0 = data is not ready. respond with nak fresum ? force resume this read/write bit forces a resume state (k or non-idle state) onto the usb data lines to initiate a remote wakeup. software should control the timing of the forced resume to be between 10 and 15 ms. setting this bit will not cause the resumf bit to be set. 1 = force data lines to k state 0 = default tp1siz3 ? tp1siz0 ? endpoint 1 transmit data packet size these read/write bits store the number of transmit data bytes for the next in token request for endpoint 1. these bits are cleared by reset. 11.8.7 usb control register 2 t2seq ? endpoint 2 transmit sequence bit this read/write bit determines which type of data packet (data0 or data1) will be sent during the next in transaction directed to endpoint 2. toggling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active for next endpoint 2 transmit 0 = data0 token active for next endpoint 2 transmit address: $0019 bit 7654321bit 0 read: t2seq stall2 tx2e rx2e tp2siz3 tp2siz2 tp2siz1 tp2siz0 write: reset:00000000 figure 11-21. usb control register 2 (ucr2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 192 universal serial bus module (usb) motorola stall2 ? endpoint 2 force stall bit this read/write bit causes endpoint 2 to return a stall handshake when polled by either an in or out token by the usb host controller. reset clears this bit. 1 = send stall handshake 0 = default tx2e ? endpoint 2 transmit enable this read/write bit enables a transmit to occur when the usb host controller sends an in token to endpoint 2. the appropriate endpoint enable bit, enable2 bit in the ucr3 register, also should be set. software should set the tx2e bit when data is ready to be transmitted. it must be cleared by software when no more data needs to be transmitted. if this bit is 0 or the txd2f is set, the usb will respond with a nak handshake to any endpoint 2 directed in tokens. reset clears this bit. 1 = data is ready to be sent 0 = data is not ready. respond with nak rx2e ? endpoint 2 receive enable this read/write bit enables a receive to occur when the usb host controller sends an out token to endpoint 2. software should set this bit when data is ready to be received. it must be cleared by software when data cannot be received. if this bit is 0 or the rxd2f is set, the usb will respond with a nak handshake to any endpoint 2 out tokens. reset clears this bit. 1 = data is ready to be received 0 = not ready for data. respond with nak tp2siz3 ? tp2siz0 ? endpoint 2 transmit data packet size these read/write bits store the number of transmit data bytes for the next in token request for endpoint 2. these bits are cleared by reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 193 11.8.8 usb control register 3 tx1st ? endpoint 0 transmit first flag this read-only bit is set if the endpoint 0 data transmit flag (txd0f) is set when the usb control logic is setting the endpoint 0 data receive flag (rxd0f). in other words, if an unserviced endpoint 0 transmit flag is still set at the end of an endpoint 0 reception, then this bit will be set. this bit lets the firmware know that the endpoint 0 transmission happened before the endpoint 0 reception. reset clears this bit. 1 = in transaction occurred before setup/out 0 = in transaction occurred after setup/out tx1str ? clear endpoint 0 transmit first flag writing a logic 1 to this write-only bit will clear the tx1st bit if it is set. writing a logic 0 to the tx1str has no effect. reset clears this bit. ostall0 ? endpoint 0 force stall bit for out token this read/write bit causes endpoint 0 to return a stall handshake when polled by an out token by the usb host controller. the usb hardware clears this bit when a setup token is received. reset clears this bit. 1 = send stall handshake 0 = default address: $001a bit 7654321bit 0 read: tx1st 0 ostall0 istall0 0 pullen enable2 enable1 write: tx1str reset:000000*00 = unimplemented * pullen bit is reset by por or lvi reset only. figure 11-22. usb control register 3 (ucr3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 194 universal serial bus module (usb) motorola istall0 ? endpoint 0 force stall bit for in token this read/write bit causes endpoint 0 to return a stall handshake when polled by an in token by the usb host controller. the usb hardware clears this bit when a setup token is received. reset clears this bit. 1 = send stall handshake 0 = default pullen ? pull-up enable this read/write bit controls the pull-up option for the usb d ? pin if the usb module is enabled. 1 = configure d ? pin to have internal pull-up 0 = disconnect d ? pin internal pull-up enable2 ? endpoint 2 enable this read/write bit enables endpoint 2 and allows the usb to respond to in or out packets addressed to endpoint 2. reset clears this bit. 1 = endpoint 2 is enabled and can respond to an in or out token 0 = endpoint 2 is disabled enable1 ? endpoint 1 enable this read/write bit enables endpoint 1 and allows the usb to respond to in packets addressed to endpoint 1. reset clears this bit. 1 = endpoint 1 is enabled and can respond to an in token 0 = endpoint 1 is disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 195 11.8.9 usb control register 4 usb control register 4 directly controls the usb data pins d+ and d ? . if the fusbo bit, and the usben bit of the usb address register (uaddr) are set, the output buffers of the usb modules are enabled and the corresponding levels of the usb data pins d+ and d ? are equal to the values set by the fdp and the fdm bits. fusbo ? force usb output this read/write bit enables the usb output buffers. 1 = enables usb output buffers 0 = usb module in normal operation fdp ? force d+ this read/write bit determinates the output level of d+. 1 = d+ at output high level 0 = d+ at output low level fdm ? force d ? this read/write bit determinates the output level of d ? . 1 = d ? at output high level 0 = d ? at output low level note: customers must be very careful when setting the ucr4 register. when the fusbo and the usben bits are set, the usb module is in output mode and it will not recognize any usb signals including the usb reset signal. the ucr4 register is used for some special applications. customers are not normally expected to use this register. address: $001b bit 7654321bit 0 read: 0 0 0 0 0 fusbo fdp fdm write: reset:00000000 = unimplemented figure 11-23. usb control register 4 (ucr4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 196 universal serial bus module (usb) motorola 11.8.10 usb status register 0 r0seq ? endpoint 0 receive sequence bit this read-only bit indicates the type of data packet last received for endpoint 0 (data0 or data1). 1 = data1 token received in last endpoint 0 receive 0 = data0 token received in last endpoint 0 receive setup ? setup token detect bit this read-only bit indicates that a valid setup token has been received. 1 = last token received for endpoint 0 was a setup token 0 = last token received for endpoint 0 was not a setup token rp0siz3 ? rp0siz0 ? endpoint 0 receive data packet size these read-only bits store the number of data bytes received for the last out or setup transaction for endpoint 0. address: $003d bit 7654321bit 0 read: r0seq setup 0 0 rp0siz3 rp0siz2 rp0siz1 rp0siz0 write: reset: unaffected by reset = unimplemented figure 11-24. usb status register 0 (usr0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 197 11.8.11 usb status register 1 r2seq ? endpoint 2 receive sequence bit this read-only bit indicates the type of data packet last received for endpoint 2 (data0 or data1). 1 = data1 token received in last endpoint 2 receive 0 = data0 token received in last endpoint 2 receive txack ? ack token transmit bit this read-only bit indicates that an ack token has been transmitted. this bit is updated at the end of the data transmission. 1 = last token transmitted for endpoint 0 was an ack token 0 = last token transmitted for endpoint 0 was not an ack token txnak ? nak token transmit bit this read-only bit indicates that a txnak token has been transmitted. this bit is updated at the end of the data transmission. 1 = last token transmitted for endpoint 0 was a nak token 0 = last token transmitted for endpoint 0 was not a nak token txstl ? stall token transmit bit this read-only bit indicates that a stall token has been transmitted. this bit is updated at the end of the data transmission. 1 = last token transmitted for endpoint 0 was a stall token 0 = last token transmitted for endpoint 0 was not a stall token rp2siz3 ? rp2siz0 ? endpoint 2 receive data packet size these read-only bits store the number of data bytes received for the last out transaction for endpoint 2. address: $003e bit 7654321bit 0 read: r2seq txack txnak txstl rp2siz3 rp2siz2 rp2siz1 rp2siz0 write: reset:u0 0 0uuuu = unimplemented u = unaffected by reset figure 11-25. usb status register 2 (usr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 198 universal serial bus module (usb) motorola 11.8.12 usb endpoint 0 data registers ue0rx7 ? ue0rx0 ? endpoint 0 receive data buffer these read-only bits are serially loaded with out token or setup token data directed at endpoint 0. the data is received over the usb ? s d+ and d ? pins. ue0tx7 ? ue0tx0 ? endpoint 0 transmit data buffer these write-only buffers are loaded by software with data to be sent on the usb bus on the next in token directed at endpoint 0. address: $0020 ue0d0 bit 7654321bit 0 read: ue0r07 ue0r06 ue0r05 ue0r04 ue0r03 ue0r02 ue0r01 ue0r00 write: ue0t07 ue0t06 ue0t05 ue0t04 ue0t03 ue0t02 ue0t01 ue0t00 reset: unaffected by reset address: $0027 ue0d7 read: ue0r77 ue0r76 ue0r75 ue0r74 ue0r73 ue0r72 ue0r71 ue0r70 write: ue0t77 ue0t76 ue0t75 ue0t74 ue0t73 ue0t72 ue0t71 ue0t70 reset: unaffected by reset figure 11-26. usb endpoint 0 data registers (ue0d0 ? ue0d7) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 199 11.8.13 usb endpoint 1 data registers ue1tx7 ? ue1tx0 ? endpoint 1 transmit or receive data buffer these write-only buffers are loaded by software with data to be sent on the usb bus on the next in token directed at endpoint 1. address: $0028 ue1d0 bit 7654321bit 0 read: write: ue1t07 ue1t06 ue1t05 ue1t04 ue1t03 ue1t02 ue1t01 ue1t00 reset: unaffected by reset address: $002f ue1d7 read: write: ue1t77 ue1t76 ue1t75 ue1t74 ue1t73 ue1t72 ue1t71 ue1t70 reset: unaffected by reset = unimplemented figure 11-27. usb endpoint 1 data registers (ue1d0 ? ue1d7) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 200 universal serial bus module (usb) motorola 11.8.14 usb endpoint 2 data registers ue2rx7 ? ue2rx0 ? endpoint 2 receive data buffer these read-only bits are serially loaded with out token data directed at endpoint 2. the data is received over the usb ? s d+ and d ? pins. ue2tx7 ? ue2tx0 ? endpoint 2 transmit data buffer these write-only buffers are loaded by software with data to be sent on the usb bus on the next in token directed at endpoint 2. address: $0030 ue2d0 bit 7654321bit 0 read: ue2r07 ue2r06 ue2r05 ue2r04 ue2r03 ue2r02 ue2r01 ue2r00 write: ue2t07 ue2t06 ue2t05 ue2t04 ue2t03 ue2t02 ue2t01 ue2t00 reset: unaffected by reset address: $0037 ue2d7 read: ue2r77 ue2r76 ue2r75 ue2r74 ue2r73 ue2r72 ue2r71 ue2r70 write: ue2t77 ue2t76 ue2t75 ue2t74 ue2t73 ue2t72 ue2t71 ue2t70 reset: unaffected by reset figure 11-28. usb endpoint 2 data registers (ue2d0 ? ue2d7) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) usb interrupts MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 201 11.9 usb interrupts the usb module is capable of generating interrupts and causing the cpu to execute the usb interrupt service routine. there are three types of usb interrupts: end-of-transaction interrupts signify either a completed transaction receive or transmit transaction. resume interrupts signify that the usb bus is reactivated after having been suspended. end-of-packet interrupts signify that a low-speed end-of-packet signal was detected. all usb interrupts share the same interrupt vector. firmware is responsible for determining which interrupt is active. 11.9.1 usb end-of-transaction interrupt there are five possible end-of-transaction interrupts: endpoint 0 or 2 receive endpoint 0, 1 or 2 transmit end-of-transaction interrupts occur as detailed in the following sections. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 202 universal serial bus module (usb) motorola 11.9.1.1 receive control endpoint 0 for a control out transaction directed at endpoint 0, the usb module will generate an interrupt by setting the rxd0f flag in the uir0 register. the conditions necessary for the interrupt to occur are shown in the flowchart in figure 11-29 . figure 11-29. out token data flow for receive endpoint 0 valid out token received for endpoint 0 error free data packet? no response from usb function set rxd0f to 1 (rxd0ie = 1) no interrupt accept data no response from usb function timeout n set/clear r0seq bit valid data token received for endpoint 0? usb module enabled? (usben = 1) endpoint 0 receive not stalled? (ostall0 = 0) endpoint 0 receive ready to receive? (rx0e = 1) and (rxd0f = 0) receive control endpoint interrupt enabled? valid transaction interrupt generated send stall handshake send nak handshake no response from usb function ignore transaction y y y y y y n n n n n y f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) usb interrupts MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 203 setup transactions cannot be stalled by the usb function. a setup received by a control endpoint will clear the istall0 and ostall0 bits. the conditions for receiving a setup interrupt are shown in figure 11-30 . figure 11-30. setup token data flow for receive endpoint 0 error free data packet? no response from usb function set rxd0f to 1 (rxd0ie = 1) no interrupt accept data n set/clear r0seq bit valid setup token received for endpoint 0? usb module enabled? (usben = 1) endpoint 0 receive ready to receive? (rx0e = 1) and (rxd0f = 0) receive control endpoint interrupt enabled? valid transaction interrupt generated no response from usb function no response from usb function ignore transaction y y y y y n n n set setup bit to 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 204 universal serial bus module (usb) motorola 11.9.1.2 transmit control endpoint 0 for a control in transaction directed at endpoint 0, the usb module will generate an interrupt by setting the txd0f flag in the uir1 register. the conditions necessary for the interrupt to occur are shown in the flowchart in figure 11-31 . figure 11-31. in token data flow for transmit endpoint 0 valid in token received for endpoint 0 send stall handshake set txd0f to 1 (txd0ie = 1) no interrupt send data n data pid set by t0seq usb module enabled? (usben = 1) transmit endpoint not stalled by firmware (istall0 = 0)? transmit endpoint ready to transfer? (tx0e = 1) and (txd0f = 0) transmit endpoint interrupt enabled? valid transaction interrupt generated send nak handshake y y y y y n n n n y no response from usb function ack received and no timeout condition occurs? no response from usb function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) usb interrupts MC68HC908JB16 ? rev. 1.0 technical data motorola universal serial bus module (usb) 205 11.9.1.3 transmit endpoint 1 for an in transaction directed at endpoint 1, the usb module will generate an interrupt by setting the txd1f in the uir1 register. the conditions necessary for the interrupt to occur are shown in figure 11-32 . figure 11-32. in token data flow for transmit endpoint 1 valid in token received for endpoint 1 send stall handshake set txd1f to 1 (txd1ie = 1) no interrupt send data n data pid set by t1seq usb module enabled? (usben = 1) transmit endpoint not stalled by firmware (stall1 = 1)? transmit endpoint ready to transfer? (tx1e = 1) and (txd1f = 0) and (ue1tr = 0) transmit endpoint enabled? (enable = 1) transmit endpoint interrupt enabled? valid transaction interrupt generated send nak handshake no response from usb function y y y y y y n n n n n y no response from usb function ack received and no timeout condition occurs? no response from usb function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data MC68HC908JB16 ? rev. 1.0 206 universal serial bus module (usb) motorola 11.9.1.4 transmit endpoint 2 for an in transaction directed at endpoint 2, the usb module will generate an interrupt by setting the txd2f in the uir1 register. 11.9.1.5 receive endpoint 2 for an out transaction directed at endpoint 2, the usb module will generate an interrupt by setting the rxd2f in the uir1 register. 11.9.2 resume interrupt the usb module will generate a cpu interrupt if low-speed bus activity is detected after entering the suspend state. a transition of the usb data lines to the non-idle state (k state) while in the suspend mode will set the resumf flag in the uir1 register. there is no interrupt enable bit for this interrupt source and an interrupt will be executed if the i-bit in the ccr is cleared. a resume interrupt can only occur while the mcu is in the suspend mode. 11.9.3 end-of-packet interrupt the usb module can generate a usb interrupt upon detection of an end-of-packet signal for low-speed devices. upon detection of an end- of-packet signal, the usb module sets the eopf bit and will generate a cpu interrupt if the eopie bit in the uir0 register is set. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 207 technical data ? MC68HC908JB16 section 12. serial communications interface module (sci) 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.5.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 12.5.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 12.5.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 12.5.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . 215 12.5.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.5.2.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.5.2.5 inversion of transmitted output. . . . . . . . . . . . . . . . . . . 217 12.5.2.6 transmitter interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 217 12.5.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 12.5.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 12.5.3.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . .218 12.5.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 12.5.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 12.5.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .222 12.5.3.6 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12.5.3.7 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 12.5.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 12.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 12.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 12.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 12.7 sci during break module interrupts. . . . . . . . . . . . . . . . . . . . 228 12.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 12.8.1 txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 208 serial communications interface module (sci) motorola 12.8.2 rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 12.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 12.9.1 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 12.9.2 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 12.9.3 sci control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 12.9.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 12.9.5 sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 12.9.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 12.9.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 12.2 introduction this section describes the serial communications interface (sci) module, which allows high-speed asynchronous communications with peripheral devices and other mcus. note: references to dma (direct-memory access) and associated functions are only valid if the mcu has a dma module. this mcu does not have the dma function. any dma-related register bits should be left in their reset state for normal mcu operation. 12.3 features features of the sci module include the following: full-duplex operation standard mark/space non-return-to-zero (nrz) format 32 programmable baud rates programmable 8-bit or 9-bit character length separately enabled transmitter and receiver separate receiver and transmitter cpu interrupt requests programmable transmitter output polarity baud rate clock source is oscdclk (2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) features MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 209 two receiver wakeup methods: ? idle line wakeup ? address mark wakeup interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framing error detection hardware parity checking 1/16 bit-time noise detection f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 210 serial communications interface module (sci) motorola 12.4 pin name conventions the generic names of the sci i/o pins are: rxd (receive data) txd (transmit data) sci i/o (input/output) lines are implemented by sharing parallel i/o port pins. the full name of an sci input or output reflects the name of the shared port pin. table 12-1 shows the full names and the generic names of the sci i/o pins. the generic pin names appear in the text of this section. 12.5 functional description figure 12-1 shows the structure of the sci module. the sci allows full- duplex, asynchronous, nrz serial communication among the mcu and remote devices, including other mcus. the transmitter and receiver of the sci operate independently, although they use the same baud rate generator. during normal operation, the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. the baud rate clock source for the sci is the oscdclk from the oscillator circuit, which is two times the crystal clock, oscxclk. table 12-1. pin name conventions generic pin names: rxd txd full pin names: ptc1/rxd ptc0/txd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 211 figure 12-1. sci module block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 dmate orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register dma interrupt control transmitter interrupt control receiver interrupt control error interrupt control control dmare ensci loops ensci internal bus txinv loops 3 16 pre- scaler baud divider rxd txd oscdclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 212 serial communications interface module (sci) motorola addr.register name bit 7654321bit 0 $005a sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $005b sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $005c sci control register 3 (scc3) read: r8 t8 dmare dmate orie neie feie peie write: reset:uu000000 $005d sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset:11000000 $005e sci status register 2 (scs2) read: bkf rpf write: reset:00000000 $005f sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0060 sci baud rate register (scbr) read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:0000 000 = unimplemented r = reserved u = unaffected figure 12-2. sci i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 213 12.5.1 data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 12-3 . figure 12-3. sci data formats 12.5.2 transmitter figure 12-4 shows the structure of the sci transmitter. the baud rate clock source for the sci is the oscdclk. bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format bit m in scc1 clear start bit bit 0 next stop bit start bit 9-bit data format bit m in scc1 set bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 parity bit parity bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 214 serial communications interface module (sci) motorola figure 12-4. sci transmitter dmate scte pen pty h876543210l 11-bit transmit stop start t8 dmate scte sctie tcie sbk tc parity generation msb sci data register load from scdr shift enable preamble all 1s break all 0s transmitter control logic shift register dmate tc sctie tcie scte transmitter cpu interrupt request transmitter dma service request m ensci loops te txinv internal bus 3 pre- scaler scp1 scp0 scr2 scr1 scr0 baud divider 16 sctie txd oscdclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 215 12.5.2.1 character length the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when transmitting 9-bit data, bit t8 in sci control register 3 (scc3) is the ninth bit (bit 8). 12.5.2.2 character transmission during an sci transmission, the transmit shift register shifts a character out to the txd pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift register. to initiate an sci transmission: 1. enable the sci by writing a logic 1 to the enable sci bit (ensci) in sci control register 1 (scc1). 2. enable the transmitter by writing a logic 1 to the transmitter enable bit (te) in sci control register 2 (scc2). 3. clear the sci transmitter empty bit by first reading sci status register 1 (scs1) and then writing to the scdr. 4. repeat step 3 for each subsequent transmission. at the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s. after the preamble shifts out, control logic transfers the scdr data into the transmit shift register. a logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. a logic 1 stop bit goes into the most significant bit position. the sci transmitter empty bit, scte, in scs1 becomes set when the scdr transfers a byte to the transmit shift register. the scte bit indicates that the scdr can accept new data from the internal data bus. if the sci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmitter cpu interrupt request. when the transmit shift register is not transmitting a character, the txd pin goes to the idle condition, logic 1. if at any time software clears the ensci bit in sci control register 1 (scc1), the transmitter and receiver relinquish control of the port pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 216 serial communications interface module (sci) motorola 12.5.2.3 break characters writing a logic 1 to the send break bit, sbk, in scc2 loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the m bit in scc1. as long as sbk is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. after software clears the sbk bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. the automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. the sci recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. receiving a break character has these effects on sci registers: sets the framing error bit (fe) in scs1 sets the sci receiver full bit (scrf) in scs1 clears the sci data register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception in progress flag (rpf) bits 12.5.2.4 idle characters an idle character contains all logic 1s and has no start, stop, or parity bit. idle character length depends on the m bit in scc1. the preamble is a synchronizing idle character that begins every transmission. if the te bit is cleared during a transmission, the txd pin becomes idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the character currently being transmitted. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 217 note: when queueing an idle character, return the te bit to logic 1 before the stop bit of the current character shifts out to the txd pin. setting te after the stop bit appears on txd causes data previously written to the scdr to be lost. toggle the te bit for a queued idle character when the scte bit becomes set and just before writing the next byte to the scdr. 12.5.2.5 inversion of transmitted output the transmit inversion bit (txinv) in sci control register 1 (scc1) reverses the polarity of transmitted data. all transmitted values, including idle, break, start, and stop bits, are inverted when txinv is at logic 1. (see 12.9.1 sci control register 1 .) 12.5.2.6 transmitter interrupts these conditions can generate cpu interrupt requests from the sci transmitter: sci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can generate a transmitter cpu interrupt request. setting the sci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generate transmitter cpu interrupt requests. transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the transmission complete interrupt enable bit, tcie, in scc2 enables the tc bit to generate transmitter cpu interrupt requests. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 218 serial communications interface module (sci) motorola 12.5.3 receiver figure 12-5 shows the structure of the sci receiver. 12.5.3.1 character length the receiver can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bit data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). 12.5.3.2 character reception during an sci reception, the receive shift register shifts characters in from the rxd pin. the sci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive shift register, the data portion of the character transfers to the scdr. the sci receiver full bit, scrf, in sci status register 1 (scs1) becomes set, indicating that the received byte can be read. if the sci receive interrupt enable bit, scrie, in scc2 is also set, the scrf bit generates a receiver cpu interrupt request. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 219 figure 12-5. sci receiver block diagram all 1s all 0s m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery dmare scrf or orie nf neie fe feie pe peie dmare scrie scrf ilie idle wakeup logic parity checking msb error cpu interrupt request dma service request cpu interrupt request sci data register r8 dmare orie neie feie peie scrie ilie rwu scrf idle or nf fe pe internal bus pre- scaler baud divider 3 16 scp1 scp0 scr2 scr1 scr0 scrie dmare oscdclk rxd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 220 serial communications interface module (sci) motorola 12.5.3.3 data sampling the receiver samples the rxd pin at the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at the following times (see figure 12-6 ): after every start bit after the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. figure 12-6. receiver data sampling rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb rxd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 221 to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 12-2 summarizes the results of the start bit verification samples. start bit verification is not successful if any two of the three verification samples are logic 1s. if start bit verification is not successful, the rt clock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 12-3 summarizes the results of the data bit samples. table 12-2. start bit verification rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 table 12-3. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 222 serial communications interface module (sci) motorola note: the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verification, the noise flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 12-4 summarizes the results of the stop bit samples. 12.5.3.4 framing errors if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. a break character also sets the fe bit because a break character has no stop bit. the fe bit is set at the same time that the scrf bit is set. 12.5.3.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. then a noise error occurs. if more than one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate table 12-4. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 223 tolerance is much more than the degree of misalignment that is likely to occur. as the receiver samples an incoming character, it resynchronizes the rt clock on any valid falling edge within the character. resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. slow data tolerance figure 12-7 shows how much a slow received character can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 12-7. slow data for an 8-bit character, data sampling of the stop bit takes the receiver 9bit times ? 154 ------------------------- - 100 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 224 serial communications interface module (sci) motorola with the misaligned character shown in figure 12-7 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 10 bit times ? 170 ------------------------- - 100 ? 154 ------------------------- - 100 = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 225 for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 12.5.3.6 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in scc2 puts the receiver into a standby state during which receiver interrupts are disabled. depending on the state of the wake bit in scc1, either of two conditions on the rxd pin can bring the receiver out of the standby state: address mark ? an address mark is a logic 1 in the most significant bit position of a received character. when the wake bit is set, an address mark wakes the receiver from the standby state by clearing the rwu bit. the address mark also sets the sci receiver full bit, scrf. software can then compare the character containing the address mark to the user-defined address of the receiver. if they are the same, the receiver remains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. idle input line condition ? when the wake bit is clear, an idle character on the rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the sci receiver 170 176 ? 170 ------------------------- - 100 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 226 serial communications interface module (sci) motorola full bit, scrf. the idle line type bit, ilty, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. note: with the wake bit clear, setting the rwu bit after the rxd pin has been idle may cause the receiver to wake up immediately. 12.5.3.7 receiver interrupts the following sources can generate cpu interrupt requests from the sci receiver: sci receiver full (scrf) ? the scrf bit in scs1 indicates that the receive shift register has transferred a character to the scdr. scrf can generate a receiver cpu interrupt request. setting the sci receive interrupt enable bit, scrie, in scc2 enables the scrf bit to generate receiver cpu interrupts. idle input (idle) ? the idle bit in scs1 indicates that 10 or 11 consecutive logic 1s shifted in from the rxd pin. the idle line interrupt enable bit, ilie, in scc2 enables the idle bit to generate cpu interrupt requests. 12.5.3.8 error interrupts the following receiver error flags in scs1 can generate cpu interrupt requests: receiver overrun (or) ? the or bit indicates that the receive shift register shifted in a new character before the previous character was read from the scdr. the previous character remains in the scdr, and the new character is lost. the overrun interrupt enable bit, orie, in scc3 enables or to generate sci error cpu interrupt requests. noise flag (nf) ? the nf bit is set when the sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, in scc3 enables nf to generate sci error cpu interrupt requests. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) low-power modes MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 227 framing error (fe) ? the fe bit in scs1 is set when a logic 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate sci error cpu interrupt requests. parity error (pe) ? the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in scc3 enables pe to generate sci error cpu interrupt requests. 12.6 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 12.6.1 wait mode the sci module remains active after the execution of a wait instruction. in wait mode, the sci module registers are not accessible by the cpu. any enabled cpu interrupt request from the sci module can bring the mcu out of wait mode. if sci module functions are not required during wait mode, reduce power consumption by disabling the module before executing the wait instruction. refer to 8.7 low-power modes for information on exiting wait mode. 12.6.2 stop mode the sci module is inactive after the execution of a stop instruction. the stop instruction does not affect sci register states. sci module operation resumes after an external interrupt. because the internal clock is inactive during stop mode, entering stop mode during an sci transmission or reception results in invalid data. refer to 8.7 low-power modes for information on exiting stop mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 228 serial communications interface module (sci) motorola 12.7 sci during break module interrupts the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. 12.8 i/o signals port c shares two of its pins with the sci module. the two sci i/o pins are: ptc0/txd ? transmit data ptc1/rxd ? receive data 12.8.1 txd (transmit data) the ptc0/txd pin is the serial data output from the sci transmitter. the sci shares the ptc0/txd pin with port c. when the sci is enabled, the ptc0/txd pin is an output regardless of the state of the ddrc0 bit in data direction register c (ddrc). 12.8.2 rxd (receive data) the ptc1/rxd pin is the serial data input to the sci receiver. the sci shares the ptc1/rxd pin with port c. when the sci is enabled, the ptc1/rxd pin is an input regardless of the state of the ddrc1 bit in data direction register c (ddrc). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 229 12.9 i/o registers these i/o registers control and monitor sci operation: sci control register 1 (scc1) sci control register 2 (scc2) sci control register 3 (scc3) sci status register 1 (scs1) sci status register 2 (scs2) sci data register (scdr) sci baud rate register (scbr) 12.9.1 sci control register 1 sci control register 1: enables loop mode operation enables the sci controls output polarity controls character length controls sci wakeup method controls idle character detection enables parity function controls parity type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 230 serial communications interface module (sci) motorola loops ? loop mode select bit this read/write bit enables loop mode operation. in loop mode the rxd pin is disconnected from the sci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable sci bit this read/write bit enables the sci and the sci baud rate generator. clearing ensci sets the scte and tc bits in sci status register 1 and disables transmitter interrupts. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled txinv ? transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter output not inverted note: setting the txinv bit inverts all transmitted values, including idle, break, start, and stop bits. address: $005a bit 7654321bit 0 read: loops ensci txinv m wake ilty pen pty write: reset:00000000 figure 12-9. sci control register 1 (scc1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 231 m ? mode (character length) bit this read/write bit determines whether sci characters are eight or nine bits long. (see table 12-5 .) the ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake ? wakeup condition bit this read/write bit determines which condition wakes up the sci: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty ? idle line type bit this read/write bit determines when the sci starts counting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit count begins after stop bit 0 = idle character bit count begins after start bit pen ? parity enable bit this read/write bit enables the sci parity function. (see table 12-5 .) when enabled, the parity function inserts a parity bit in the most significant bit position. (see figure 12-3 .) reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 232 serial communications interface module (sci) motorola pty ? parity bit this read/write bit determines whether the sci generates and checks for odd parity or even parity. (see table 12-5 .) reset clears the pty bit. 1 = odd parity 0 = even parity note: changing the pty bit in the middle of a transmission or reception can generate a parity error. 12.9.2 sci control register 2 sci control register 2: enables the following cpu interrupt requests: ? enables the scte bit to generate transmitter cpu interrupt requests ? enables the tc bit to generate transmitter cpu interrupt requests ? enables the scrf bit to generate receiver cpu interrupt requests ? enables the idle bit to generate receiver cpu interrupt requests table 12-5. character format selection control bits character format m pen and pty start bits data bits parity stop bits character length 0 0x 1 8 none 1 10 bits 1 0x 1 9 none 1 11 bits 0 10 1 7 even 1 10 bits 0 11 1 7 odd 1 10 bits 1 10 1 8 even 1 11 bits 1 11 1 8 odd 1 11 bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 233 enables the transmitter enables the receiver enables sci wakeup transmits sci break characters sctie ? sci transmit interrupt enable bit this read/write bit enables the scte bit to generate sci transmitter cpu interrupt requests. reset clears the sctie bit. 1 = scte enabled to generate cpu interrupt 0 = scte not enabled to generate cpu interrupt tcie ? transmission complete interrupt enable bit this read/write bit enables the tc bit to generate sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ? sci receive interrupt enable bit this read/write bit enables the scrf bit to generate sci receiver cpu interrupt requests. reset clears the scrie bit. 1 = scrf enabled to generate cpu interrupt 0 = scrf not enabled to generate cpu interrupt ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to generate sci receiver cpu interrupt requests. reset clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabled to generate cpu interrupt requests address: $005b bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 12-10. sci control register 2 (scc2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 234 serial communications interface module (sci) motorola te ? transmitter enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the txd pin. if software clears the te bit, the transmitter completes any transmission in progress before the txd returns to the idle condition (logic 1). clearing and then setting te during a transmission queues an idle character to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitter enabled 0 = transmitter disabled note: writing to the te bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. re ? receiver enable bit setting this read/write bit enables the receiver. clearing the re bit disables the receiver but does not affect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note: writing to the re bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. rwu ? receiver wakeup bit this read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the rwu bit. reset clears the rwu bit. 1 = standby state 0 = normal operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 235 sbk ? send break bit setting and then clearing this read/write bit transmits a break character followed by a logic 1. the logic 1 after the break character guarantees recognition of a valid start bit. if sbk remains set, the transmitter continuously transmits break characters with no logic 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break characters being transmitted note: do not toggle the sbk bit immediately after setting the scte bit. toggling sbk before the preamble begins causes the sci to send a break character instead of a preamble. 12.9.3 sci control register 3 sci control register 3: stores the ninth sci data bit received and the ninth sci data bit to be transmitted enables these interrupts: ? receiver overrun interrupts ? noise error interrupts ? framing error interrupts parity error interrupts address: $005c bit 7654321bit 0 read: r8 t8 dmare dmate orie neie feie peie write: reset:uu000000 = unimplemented u = unaffected figure 12-11. sci control register 3 (scc3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 236 serial communications interface module (sci) motorola r8 ? received bit 8 when the sci is receiving 9-bit characters, r8 is the read-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other 8 bits. when the sci is receiving 8-bit characters, r8 is a copy of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ? transmitted bit 8 when the sci is transmitting 9-bit characters, t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift register at the same time that the scdr is loaded into the transmit shift register. reset has no effect on the t8 bit. dmare ? dma receive enable bit caution: the dma module is not included on this mcu. writing a logic 1 to dmare or dmate may adversely affect mcu performance. 1 = dma not enabled to service sci receiver dma service requests generated by the scrf bit (sci receiver cpu interrupt requests enabled) 0 = dma not enabled to service sci receiver dma service requests generated by the scrf bit (sci receiver cpu interrupt requests enabled) dmate ? dma transfer enable bit caution: the dma module is not included on this mcu. writing a logic 1 to dmare or dmate may adversely affect mcu performance. 1 = scte dma service requests enabled; scte cpu interrupt requests disabled 0 = scte dma service requests disabled; scte cpu interrupt requests enabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 237 orie ? receiver overrun interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt requests from or bit enabled 0 = sci error cpu interrupt requests from or bit disabled neie ? receiver noise error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the noise error bit, ne. reset clears neie. 1 = sci error cpu interrupt requests from ne bit enabled 0 = sci error cpu interrupt requests from ne bit disabled feie ? receiver framing error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt requests from fe bit disabled peie ? receiver parity error interrupt enable bit this read/write bit enables sci receiver cpu interrupt requests generated by the parity error bit, pe. (see 12.9.4 sci status register 1 .) reset clears peie. 1 = sci error cpu interrupt requests from pe bit enabled 0 = sci error cpu interrupt requests from pe bit disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 238 serial communications interface module (sci) motorola 12.9.4 sci status register 1 sci status register 1 (scs1) contains flags to signal these conditions: transfer of scdr data to transmit shift register complete transmission complete transfer of receive shift register data to scdr complete receiver input idle receiver overrun noisy data framing error parity error scte ? sci transmitter empty bit this clearable, read-only bit is set when the scdr transfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an sci transmitter cpu interrupt request. in normal operation, clear the scte bit by reading scs1 with scte set and then writing to scdr. reset sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register address: $005d bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented figure 12-12. sci status register 1 (scs1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 239 tc ? transmission complete bit this read-only bit is set when the scte bit is set, and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is automatically cleared when data, preamble or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ? sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf can generate an sci receiver cpu interrupt request. when the scrie bit in scc2 is set, scrf generates a cpu interrupt request. in normal operation, clear the scrf bit by reading scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. idle generates an sci error cpu interrupt request if the ilie bit in scc2 is also set. clear the idle bit by reading scs1 with idle set and then reading the scdr. after the receiver is enabled, it must receive a valid character that sets the scrf bit before an idle condition can set the idle bit. also, after the idle bit has been cleared, a valid character must again set the scrf bit before an idle condition can set the idle bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active (or idle since the idle bit was cleared) or ? receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit generates an sci error cpu interrupt request if the orie f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 240 serial communications interface module (sci) motorola bit in scc3 is also set. the data in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. reset clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an overrun to occur between reads of scs1 and scdr in the flag-clearing sequence. figure 12-13 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearing sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag- clearing sequence reads byte 3 in the scdr instead of byte 2. in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag- clearing routine can check the or bit in a second read of scs1 after reading the data register. nf ? receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the rxd pin. nf generates an nf cpu interrupt request if the neie bit in scc3 is also set. clear the nf bit by reading scs1 and then reading the scdr. reset clears the nf bit. 1 = noise detected 0 = no noise detected fe ? receiver framing error bit this clearable, read-only bit is set when a logic 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 241 figure 12-13. flag clearing sequence pe ? receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 242 serial communications interface module (sci) motorola 12.9.5 sci status register 2 sci status register 2 contains flags to signal the following conditions: break character detected incoming data bkf ? break flag bit this clearable, read-only bit is set when the sci detects a break character on the rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate a cpu interrupt request. clear bkf by reading scs2 with bkf set and then reading the scdr. once cleared, bkf can become set again only after logic 1s again appear on the rxd pin followed by another break character. reset clears the bkf bit. 1 = break character detected 0 = no break character detected rpf ? reception in progress flag bit this read-only bit is set when the receiver detects a logic 0 during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. polling rpf before disabling the sci module or entering stop mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress address: $005e bit 7654321bit 0 read: bkf rpf write: reset:00000000 = unimplemented figure 12-14. sci status register 2 (scs2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 243 12.9.6 sci data register the sci data register (scdr) is the buffer between the internal data bus and the receive and transmit shift registers. r7/t7 ? r0/t0 ? receive/transmit data bits reading the sci data register accesses the read-only received data bits, r7:r0. writing to the sci data register writes the data to be transmitted, t7:t0. reset has no effect on the sci data register. note: do not use read/modify/write instructions on the sci data register. address: $005f bit 7654321bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 12-15. sci data register (scdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 244 serial communications interface module (sci) motorola 12.9.7 sci baud rate register the baud rate register (scbr) selects the baud rate for both the receiver and the transmitter. scp1 and scp0 ? sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 12-6 . reset clears scp1 and scp0. scr2 ? scr0 ? sci baud rate select bits these read/write bits select the sci baud rate divisor as shown in table 12-7 . reset clears scr2 ? scr0. address: $0060 bit 7654321bit 0 read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:0000 000 = unimplemented r = reserved figure 12-16. sci baud rate register (scbr) table 12-6. sci baud rate prescaling scp1 and scp0 prescaler divisor (pd) 00 1 01 3 10 4 11 13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola serial communications interface module (sci) 245 use this formula to calculate the sci baud rate: where: sci clock source = oscdclk pd = prescaler divisor bd = baud rate divisor table 12-8 shows the sci baud rates that can be generated with a 24mhz oscdclk (oscxclk=12mhz) as sci clock source. table 12-7. sci baud rate selection scr2, scr1, and scr0 baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate sci clock source 48 pd bd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908JB16 ? rev. 1.0 246 serial communications interface module (sci) motorola table 12-8. sci baud rate selection examples scp1 and scp0 prescaler divisor (pd) scr2, scr1, and scr0 baud rate divisor (bd) baud rate (oscdclk=24mhz) 00 1 000 1 baud rate settings not recommended 00 1 001 2 00 1 010 4 00 1 011 8 00 1 100 16 00 1 101 32 00 1 110 64 00 1 111 128 01 3 000 1 01 3 001 2 01 3 010 4 01 3 011 8 01 3 100 16 01 3 101 32 01 3 110 64 01 3 111 128 10 4 000 1 10 4 001 2 10 4 010 4 10 4 011 8 10 4 100 16 10 4 101 32 10 4 110 64 10 4 111 128 11 13 000 1 38461.54 11 13 001 2 19230.77 11 13 010 4 9615.38 11 13 011 8 4807.69 11 13 100 16 2403.85 11 13 101 32 1201.92 11 13 110 64 600.96 11 13 111 128 300.48 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola clock generator module (cgm) 247 technical data ? MC68HC908JB16 section 13. clock generator module (cgm) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 13.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.3.1 reference frequency source (oscxclk) . . . . . . . . . . . .250 13.3.2 voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . 250 13.3.3 reference divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.3.4 vco frequency divider . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.3.5 phase detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.3.6 phase detector filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.3.7 lock detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 13.4.1 cgm power supply pins (v dda , v ssa0 , v ssa1 ) . . . . . . . . 252 13.4.2 cgm1 voltage regulator out (v rega0 ) . . . . . . . . . . . . . . .252 13.4.3 cgm2 voltage regulator in (v rega1 ) . . . . . . . . . . . . . . . . 252 13.4.4 external filter capacitor pins (cgmxfc1, cgmxfc2) . . 253 13.4.5 cgm clock output pins (cgmout1, cgmout2) . . . . . . 253 13.5 cgmxfc external connections . . . . . . . . . . . . . . . . . . . . . . . 253 13.6 cgmout external connections. . . . . . . . . . . . . . . . . . . . . . . 254 13.7 calculation of vco frequency . . . . . . . . . . . . . . . . . . . . . . . . 254 13.8 programming the pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 13.9 cgm i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 13.9.1 bandwidth control register . . . . . . . . . . . . . . . . . . . . . . . . 256 13.9.2 vco control register (pvcr) . . . . . . . . . . . . . . . . . . . . . .256 13.9.3 vco and reference divider select registers high . . . . . . 257 13.9.4 vco divider select register low . . . . . . . . . . . . . . . . . . .258 13.9.5 reference divider select register low . . . . . . . . . . . . . . . 259 13.9.6 phase detector control register (pdcr) . . . . . . . . . . . . . 260 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908JB16 ? rev. 1.0 248 clock generator module (cgm) motorola 13.10 pre-defined vco output frequency settings . . . . . . . . . . . .260 13.11 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 13.11.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 13.11.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 13.2 introduction this section describes the clock generation module (cgm). the cgm operates at the frequency of the crystal, oscxclk, and generates frequencies in the 27mhz range. this frequency range is targeted for rf applications, such as in a local oscillator in a down conversion mixer receiver. this particular mcu has two clock generation modules which are denoted as cgm1 and cgm2. each cgm contains all the functional blocks for pll control of a vco. note: references to either cgm1 or cgm2 may be made in the following text by omitting the cgm number. for example, cgmout may refer generically to cgmout1 and cgmout2, and lock bit may refer to lock1 and lock2 bits. addr.register name bit 7654321bit 0 $0051 pll bandwidth control register (pbwc) read: r lock1 r pllon1 r lock2 rpllon2 write: reset:0000 $0052 vco control register (pvcr) read: vco_7 vco_6 vco_5 vco_4 vco_3 vco_2 vco_1 vco_0 write: reset:00110000 $0053 pll1 n & r divider select register high (pnrh1) read: vds1_11 vds1_10 vds1_9 vds1_8 00 rds1_9 rds1_8 write: reset:00100000 figure 13-1. cgm i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola clock generator module (cgm) 249 13.3 functional description figure 13-2 shows the structure of one cgm. there are two cgms in this mcu. the two cgms are independently programmable, with their respective outputs at the cgmout1 and cgmout2 pins. the following paragraphs describes the cgm circuit blocks and internal signals. $0054 pll1 n divider select register low (pnsl1) read: vds1_7 vds1_6 vds1_5 vds1_4 vds1_3 vds1_2 vds1_1 vds1_0 write: reset:01111101 $0055 pll1 r divider select register low (prsl1) read: rds1_7 rds1_6 rds1_5 rds1_4 rds1_3 rds1_2 rds1_1 rds1_0 write: reset:10010000 $0056 pll2 n & r divider select register high (pnrh2) read: vds2_11 vds2_10 vds2_9 vds2_8 00 rds2_9 rds2_8 write: reset:00100000 $0057 pll2 n divider select register low (pnsl1) read: vds2_7 vds2_6 vds2_5 vds2_4 vds2_3 vds2_2 vds2_1 vds2_0 write: reset:01111101 $0058 pll2 r divider select register low (prsl2) read: rds2_7 rds2_6 rds2_5 rds2_4 rds2_3 rds2_2 rds2_1 rds2_0 write: reset:10010000 $0059 phase detector control register (pdcr) read: phd_7 phd_6 phd_5 phd_4 phd_3 phd_2 phd_1 phd_0 write: reset:10010000 figure 13-1. cgm i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908JB16 ? rev. 1.0 250 clock generator module (cgm) motorola figure 13-2. cgm block diagram 13.3.1 reference frequency source (oscxclk) the oscxclk signal is a buffered output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. oscxclk is used as the reference frequency source for both cgm modules. 13.3.2 voltage controlled oscillator the vco clock frequency (cgmvclk) is generated internally and it is proportional to the controlled voltage setting by the phase detector output. the vco operating range is programmable for a wide range of frequencies and for maximum immunity to external noise. the cgmvclk signal is also the cgm output signal, cgmout. phase detector loop filter vco divider voltage controlled oscillator lock detector cgmfclk cgmvclk pll analog lock oscxclk reference divider vds[11:0] rds[9:0] v rega v dda v ssa cgmxfc cgmrclk cgmout vco_[7:0] pllon phd_[7:0] r n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola clock generator module (cgm) 251 13.3.3 reference divider the crystal oscillator frequency (oscxclk) is fed to the phase detector through a 10-bit programmable divider module r. the divider output (cgmrclk) is equal to cgmxclk divided by r and is used as the final reference signal for the phase detector. 13.3.4 vco frequency divider the vco output clock (cgmvclk) is fed to the phase detector through another 12-bit programmable divider module n. the divider output (cgmfclk) is equal to cgmvclk divided by n and it is the feedback signal for the phase detector. 13.3.5 phase detector the phase detector compares the vco feedback clock with the final reference clock. a correction pulse is generated based on the phase difference between the two signals. the loop filter then slightly alters the dc voltage on the external capacitor connected to pin cgmxfc base on the width and direction of the correction pulse. 13.3.6 phase detector filter the loop filter controls the dynamic characteristics of the pll. the loop filter can make fast or low corrections depending on whether the phase detector is unlocked or stable. 13.3.7 lock detector the lock detector compares the frequencies of the vco feedback clock, cgmfclk, and the final reference clock, cgmrclk. therefore, the speed of the lock detector is directly proportional to the final reference clock, cgmrclk. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908JB16 ? rev. 1.0 252 clock generator module (cgm) motorola 13.4 i/o signals the following paragraphs describe the cgm i/o signals. 13.4.1 cgm power supply pins (v dda , v ssa0 , v ssa1 ) v dda is the power supply pin, v ssa0 and v ssa1 are the ground pins for the analog portions of both cgms. 13.4.2 cgm1 voltage regulator out (v rega0 ) 3.3v output of the on-chip voltage regulator for analog portions. connect v rega0 directly to v rega1 as shown in figure 13-3 . 13.4.3 cgm2 voltage regulator in (v rega1 ) 3.3v input for cgm2 analog portions. connect v rega0 directly to v rega1 as shown in figure 13-3 . figure 13-3. cgm power supply connection cgm2 v rega1 c regbulk c regbypass 0.1 f v ssa1 + v rega1 > 4.7 f cgm1 v rega0 c regbulk c regbypass 0.1 f v ssa0 + v rega0 > 4.7 f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgmxfc external connections MC68HC908JB16 ? rev. 1.0 technical data motorola clock generator module (cgm) 253 13.4.4 external filter capacitor pins (cgmxfc1, cgmxfc2) the cgmxfc1 and cgmxfc2 pins are required by the loop filter to filter out phase corrections for each pll. an external filter network is connected to each pin. (see 13.5 cgmxfc external connections .) 13.4.5 cgm clock output pins (cgmout1, cgmout2) cgmout1 and cgmout2 are vco output signals. the output signals are buffered through logic stages to output pins without degrading the loop performance. 13.5 cgmxfc external connections the external filter network is critical to the stability and reaction time of the pll. the configurations shown in figure 13-4 (a) and (b) are recommended for connection to cgmxfc1 and cgmxfc2. figure 13-4. cgmxfc external connections 56 k ? 150 pf 2n2f v ssa0 (a) cgmxfc1 56 k ? 150 pf 2n2f v ssa1 (b) cgmxfc2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908JB16 ? rev. 1.0 254 clock generator module (cgm) motorola 13.6 cgmout external connections the output of cgm clock is a standard cmos output with push-pull configuration. the output logic high and low levels are specified with corresponding dc loading current (see 20.13 cgm electrical characteristics ). the transient current is mainly determined by the maximum loading capacitor value. figure 13-5. cgmout external connections 13.7 calculation of vco frequency the relationship between the vco frequency, f vclk , and the crystal reference frequency, f xclk , is: v rega cgmout v ssa r l c l v ssa v oh or v ol f vclk = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) programming the pll MC68HC908JB16 ? rev. 1.0 technical data motorola clock generator module (cgm) 255 13.8 programming the pll with the plls off (pllon = 0), use the following procedure to initialize both plls: 1. write $80 to the vco control register (pvcr). 2. write $70 to the phase detector register (pdcr). then for each pll, use the following procedure to program the vco and reference dividers: 3. write data to the vco and reference divider select register high (pnrh). 4. write data to the vco divider select register low (pnsl). 5. write data to the reference divider select register low (prsl). 6. set pllon = 1 in the bandwidth control register to enable the pll. to reprogram the pll frequency, clear the pllon bit (pllon =0) and repeat steps 3 to 6. note: do not program both plls to the same frequency. a difference of 50khz or more is recommended between the two pll outputs. 13.9 cgm i/o registers these registers control and monitor operation of the cgms: bandwidth control register (pbwc) vco control register (pvcr) pll1 vco and reference divider select register high (pnrh1) pll1 vco divider select register low (pnsl1) pll1 reference divider select register low (prsl1) pll2 vco and reference divider select register high (pnrh2) pll2 vco divider select register low (pnsl2) pll2 reference divider select register low (prsl2) phase detector control register (pdcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908JB16 ? rev. 1.0 256 clock generator module (cgm) motorola 13.9.1 bandwidth control register the bandwidth control register (pbwc) contains control/status bits for both plls. lockx ? lock indicator bit this read-only bit becomes set when the vco clock is locked (running at the programmed frequency). 1 = vco frequency correct or locked 0 = vco frequency incorrect or unlocked pllonx ? pll on bit this read/write bit activates each pll and enables the vco clock. 1 = pll on 0 = pll off 13.9.2 vco control register (pvcr) the vco control register configures the vco for both plls. vco_[7:0] ? vco control bits for both plls set vco_[7:0] = $80 for maximum performance. address: $0051 bit 7654321bit 0 read: r lock1 r pllon1 r lock2 r pllon2 write: reset: 0 0 0 0 = unimplemented r = reserved figure 13-6. pll bandwidth control register (pbcr) address: $0052 bit 7654321bit 0 read: vco_7 vco_6 vco_5 vco_4 vco_3 vco_2 vco_1 vco_0 write: reset:00110000 figure 13-7. vco control register (pvcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola clock generator module (cgm) 257 13.9.3 vco and reference divider select registers high the vco and reference divider select registers high (pnrh1 and pnrh2) contain the programming information for the high byte of vco feedback divider, n, and reference divider, r. vdsx_[11:8] ? vco divider select bits these read/write bits control the high byte of the vco feedback divider, n. rdsx_[9:8] ? reference divider select bits these read/write bits control the high byte of the reference divider, r. note: the vdsx_[11:8] and rdsx_[9:8] bits are not latched until the respective low bytes are written. address: $0053 bit 7654321bit 0 read: vds1_11 vds1_10 vds1_9 vds1_8 00 rds1_9 rds1_8 write: reset:00100000 = unimplemented figure 13-8. pll1 n & r divider select register high (pnrh1) address: $0056 bit 7654321bit 0 read: vds2_11 vds2_10 vds2_9 vds2_8 00 rds2_9 rds2_8 write: reset:00100000 = unimplemented figure 13-9. pll2 n & r divider select register high (pnrh2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908JB16 ? rev. 1.0 258 clock generator module (cgm) motorola 13.9.4 vco divider select register low the vco divider select registers low (pnsl1 and pnsl2) contain the programming information for the low byte of vco feedback divider, n. vdsx_[7:0] ? vco divider select bits these read/write bits control the low byte of the vco feedback divider, n. note: writing to pnsl also latches the respective high bits, vdsx_[11:8]. address: $0054 bit 7654321bit 0 read: vds1_7 vds1_6 vds1_5 vds1_4 vds1_3 vds1_2 vds1_1 vds1_0 write: reset:01111101 figure 13-10. pll1 n divider select register low (pnsl1) address: $0057 bit 7654321bit 0 read: vds2_7 vds2_6 vds2_5 vds2_4 vds2_3 vds2_2 vds2_1 vds2_0 write: reset:01111101 figure 13-11. pll2 n divider select register low (pnsl2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm i/o registers MC68HC908JB16 ? rev. 1.0 technical data motorola clock generator module (cgm) 259 13.9.5 reference divider select register low the divider select registers low (prsl1 and prls2) contain the programming information for the low byte of reference divider, r. rdsx_[7:0] ? reference divider select bits these read/write bits control the high byte of the reference divider, r. note: writing to prsl also latches the respective high bits, rdsx_[9:8]. address: $0055 bit 7654321bit 0 read: rds1_7 rds1_6 rds1_5 rds1_4 rds1_3 rds1_2 rds1_1 rds1_0 write: reset:10010000 figure 13-12. pll1 r divider select register low (prsl1) address: $0058 bit 7654321bit 0 read: rds2_7 rds2_6 rds2_5 rds2_4 rds2_3 rds2_2 rds2_1 rds2_0 write: reset:10010000 figure 13-13. pll2 r divider select register low (prsl2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908JB16 ? rev. 1.0 260 clock generator module (cgm) motorola 13.9.6 phase detector control register (pdcr) the phase detector control register configures the phase detector for both plls. phd_[7:0] ? phase detector control bits for both plls set phd_[7:0] = $70 for maximum performance. 13.10 pre-defined vco output frequency settings the exact frequency values for the following required channels cannot be synthesized by using a reference frequency higher than 10khz. an absolute offset frequency from +1.66khz to +1.89khz will be introduced for different channels and the maximum relative offset is only address: $0059 bit 7654321bit 0 read: phd_7 phd_6 phd_5 phd_4 phd_3 phd_2 phd_1 phd_0 write: reset:10010000 figure 13-14. phase detector control register (pdcr) table 13-1. predefined programming setting for pll channel frequency (mhz) crystal frequency (mhz) divider r reference frequency (khz) divider n vco frequency (mhz) absolute offset (khz) 26.54 12 288 41.67 637 26.54166 +1.66 26.59 12 338 35.50 749 26.59171 +1.71 26.64 12 268 44.78 595 26.64179 +1.79 26.69 12 370 32.43 823 26.69189 +1.89 26.74 12 302 39.74 673 26.74172 +1.72 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) low-power modes MC68HC908JB16 ? rev. 1.0 technical data motorola clock generator module (cgm) 261 13.11 low-power modes the wait and stop instructions put the mcu in low-power consumption standby modes. 13.11.1 wait mode the cgms remain active and all pll registers are not affected in wait mode. if cgm functions are not required in wait mode, it can be disabled by the pllonx bit in the bandwidth control register (pbwc). 13.11.2 stop mode the cgm is inactive and all pll registers are not affected in stop mode. cgm operation resumes when the mcu exits stop mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908JB16 ? rev. 1.0 262 clock generator module (cgm) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola input/output (i/o) ports 263 technical data ? MC68HC908JB16 section 14. input/output (i/o) ports 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 14.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 14.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 14.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 267 14.4 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 14.4.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 14.4.2 data direction register c. . . . . . . . . . . . . . . . . . . . . . . . . . 270 14.5 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 14.5.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 14.5.2 data direction register d. . . . . . . . . . . . . . . . . . . . . . . . . . 273 14.6 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 14.6.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 14.6.2 data direction register e. . . . . . . . . . . . . . . . . . . . . . . . . . 277 14.7 port options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 14.7.1 port option control register . . . . . . . . . . . . . . . . . . . . . . . 279 14.2 introduction twenty-one (21) bidirectional input-output (i/o) pins form four parallel ports. all i/o pins are programmable as inputs or outputs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908JB16 ? rev. 1.0 264 input/output (i/o) ports motorola note: connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 reserved read: rrrrrrrr write: reset: $0002 port c data register (ptc) read: 000000 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: 0 0 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:0*0000000 * ddra7 bit is reset by por or lvi reset only. $0005 reserved read: rrrrrrrr write: reset: $0006 data direction register c (ddrc) read: 000000 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) read: 0 0 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) read: 0 0 0 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset = unimplemented r = reserved figure 14-1. i/o port register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports introduction MC68HC908JB16 ? rev. 1.0 technical data motorola input/output (i/o) ports 265 $0009 data direction register e (ddre) read: 0 0 0 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 $001d port option control register (pocr) read: pte20p ptdldd ptdildd pte4p pte3p pcp r pap write: reset:00000000 table 14-1. port control register bits summary port bit ddr module control pin module register control bit a 0 ddra0 kbi kbier $0017 kbie0 pta0/kba0 1 ddra1 kbie1 pta1/kba1 2 ddra2 kbie2 pta2/kba2 3 ddra3 kbie3 pta3/kba3 4 ddra4 kbie4 pta4/kba4 5 ddra5 kbie5 pta5/kba5 6 ddra6 kbie6 pta6/kba6 7 ddra7 kbie7 pta7/kba7 c 0 ddrc0 sci scc1 $005a ensci ptc0/txd 1 ddrc1 ptc1/rxd d0 ? 5 ddrd[0:5] ??? ptd0 ? ptd5 e 0 ddre0 tim1 or tim2 t1sc $000a or t2sc $0040 ps[2:0] pte0/tclk 1 ddre1 tim1 t1sc0 $0010 or t1sc1 $0013 els0b:els0a or els1b:els1a pte1/t1ch01 2 ddre2 tim2 t2sc0 $0046 or t2sc1 $0049 els0b:els0a or els1b:els1a pte2/t2ch01 3 ddre3 usb uaddr $0038 usben pte3/d+ 4 ddre4 pte4/d ? addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 14-1. i/o port register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908JB16 ? rev. 1.0 266 input/output (i/o) ports motorola 14.3 port a port a is an 8-bit general-purpose bidirectional i/o port with software configurable pullups, and shares its pins with the keyboard interrupt module (kbi). 14.3.1 port a data register the port a data register contains a data latch for each of the eight port a pins. pta[7:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. the port a pullup control bit, pap, in the port option control register (pocr) enables pullups on port a pins if the respective pin is configured as an input. (see 14.7 port options .) kba7 ? kba0 ? keyboard interrupts the keyboard interrupt enable bits, kbie7 ? kbie0, in the keyboard interrupt enable register (kbier), enable the port a pins as external interrupt pins. (see section 16. keyboard interrupt module (kbi) .) address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset alternative function: kba7 kba6 kba5 kba4 kba3 kba2 kba1 kba0 additional function: optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup figure 14-2. port a data register (pta) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port a MC68HC908JB16 ? rev. 1.0 technical data motorola input/output (i/o) ports 267 14.3.2 data direction register a data direction register a determines whether each port a pin is an input or an output. writing a logic 1 to a ddra bit enables the output buffer for the corresponding port a pin; a logic 0 disables the output buffer. ddra[7:0] ? data direction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pins by writing to the port a data register before changing data direction register a bits from 0 to 1. figure 14-4 shows the port a i/o logic. figure 14-4. port a i/o circuit address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0 * 0000000 * ddra7 bit is reset by por or lvi reset only. figure 14-3. data direction register a (ddra) read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908JB16 ? rev. 1.0 268 input/output (i/o) ports motorola when bit ddrax is a logic 1, reading address $0000 reads the ptax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 14-2 summarizes the operation of the port a pins. table 14-2. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0 x (1) notes : 1. x = don ? t care. input, hi-z (2) 2. hi-z = high impedance. ddra[7:0] pin pta[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddra[7:0] pta[7:0] pta[7:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port c MC68HC908JB16 ? rev. 1.0 technical data motorola input/output (i/o) ports 269 14.4 port c port c is a 2-bit special function port that shares its pins with the serial communications interface (sci) module. these pins have software configurable pullups. 14.4.1 port c data register the port c data register contains a data latch for each of the two port c pins. ptc[1:0] ? port c data bits these read/write bits are software-programmable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. the port c pullup enable bit, pcp, in the port option control register (pocr) enables pullups on ptc[1:0] if the respective pin is configured as an input. (see 14.7 port options .) txd, rxd ? sci data i/o pins the txd and rxd pins are the transmit data output and receive data input for the sci module. the sci enable bit, ensci, in the sci control register 1 enables the ptc0/txd and ptc1/rxd pins as sci txd and rxd pins and overrides any control from the port i/o. see section 12. serial communications interface module (sci) . address: $0002 bit 7654321bit 0 read: 000000 ptc1 ptc0 write: reset: unaffected by reset alternative function: rxd txd additional function: optional pullup optional pullup figure 14-5. port c data register (ptc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908JB16 ? rev. 1.0 270 input/output (i/o) ports motorola 14.4.2 data direction register c data direction register c determines whether each port c pin is an input or an output. writing a logic 1 to a ddrc bit enables the output buffer for the corresponding port c pin; a logic 0 disables the output buffer. ddrc[1:0] ? data direction register c bits these read/write bits control port c data direction. reset clears ddrc[1:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writing to the port c data register before changing data direction register c bits from 0 to 1. figure 14-7 shows the port c i/o logic. figure 14-7. port c i/o circuit address: $0006 bit 7654321bit 0 read: 000000 ddrc1 ddrc0 write: reset:00000000 figure 14-6. data direction register c (ddrc) read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port c MC68HC908JB16 ? rev. 1.0 technical data motorola input/output (i/o) ports 271 when bit ddrcx is a logic 1, reading address $0002 reads the ptcx data latch. when bit ddrcx is a logic 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 14-3 summarizes the operation of the port c pins. table 14-3. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0 x (1) notes : 1. x = don ? t care. input, hi-z (2) 2. hi-z = high impedance. ddrc[1:0] pin ptc[1:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrc[1:0] ptc[1:0] ptc[1:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908JB16 ? rev. 1.0 272 input/output (i/o) ports motorola 14.5 port d port d is an 6-bit general-purpose bidirectional i/o port. these pins are open-drain when configured as output. 14.5.1 port d data register the port d data register contains a data latch for each of the six port d pins. note: bits 5 ? 1 of ptd are not available in the 32-pin low-profile quad flat pack. ptd[5:0] ? port d data bits these read/write bits are software programmable. data direction of each port d pin is under control of the corresponding bit in data direction register d. reset has no effect on port d data. the led direct drive bit, ptdldd, in the port option control register (pocr) controls the drive options for ptd5 ? ptd2 pins. the infrared led drive bit, ptdildd, in the pocr controls the drive options for ptd1 ? ptd0 pins. (see 14.7 port options .) address: $0003 bit 7654321bit 0 read: 0 0 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset additional function: 10ma sink 10ma sink 10ma sink 10ma sink 25ma sink 25ma sink figure 14-8. port d data register (ptd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port d MC68HC908JB16 ? rev. 1.0 technical data motorola input/output (i/o) ports 273 14.5.2 data direction register d data direction register d determines whether each port d pin is an input or an output. writing a logic 1 to a ddrd bit enables the output buffer for the corresponding port d pin; a logic 0 disables the output buffer. ddrd[5:0] ? data direction register d bits these read/write bits control port d data direction. reset clears ddrd[5:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input port d pins are open-drain when configured as output. note: avoid glitches on port d pins by writing to the port d data register before changing data direction register d bits from 0 to 1. note: for those devices packaged in a 32-pin low-profile quad flat pack, ptd5 ? 1 are not connected. ddrd5 ? 1 should be set to a 1 to configure ptd5 ? 1 as outputs. figure 14-10 shows the port d i/o circuit logic. address: $0007 bit 7654321bit 0 read: 0 0 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 figure 14-9. data direction register d (ddrd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908JB16 ? rev. 1.0 274 input/output (i/o) ports motorola figure 14-10. port d i/o circuit when bit ddrdx is a logic 1, reading address $0003 reads the ptdx data latch. when bit ddrdx is a logic 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 14-4 summarizes the operation of the port d pins. table 14-4. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0 x (1) notes : 1. x = don ? t care. input, hi-z (2) 2. hi-z = high impedance. ddrd[5:0] pin ptd[5:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrd[5:0] ptd[5:0] ptd[5:0] read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port e MC68HC908JB16 ? rev. 1.0 technical data motorola input/output (i/o) ports 275 14.6 port e port e is a 5-bit special function port that shares three of its pins with the timer interface modules (tims) and two of its pins with the usb data pins d+ and d ? . pte4 and pte3 are open-drain when configured as output. 14.6.1 port e data register the port e data register contains a data latch for each of the five port e pins. pte[4:0] ? port e data bits pte[4:0] are read/write, software-programmable bits. data direction of each port e pin is under the control of the corresponding bit in data direction register e. the pte4 and pte3 pullup enable bits, pte4p and pte3p, in the port option control register (pocr) enable 5k ? address: $0008 bit 7654321bit 0 read: 0 0 0 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset alternative function: d ? d+ t2ch01 t1ch01 tclk additional function: optional pullup optional pullup optional pullup optional pullup optional pullup additional function: external interrupt open-drain open-drain = unimplemented figure 14-11. port e data register (pte) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908JB16 ? rev. 1.0 276 input/output (i/o) ports motorola the pte[2:0] pullup enable bit, pte20p, in the port option control register (pocr) enables pullups on pte2 ? pte0, regardless of the pin is configured as an input or an output. (see 14.7 port options .) pte4 pin functions as an external interrupt when pte4ie=1 in the irq option control register (iocr) and usben=0 in the usb address register (usb disabled). (see 15.9 irq option control register .) d ? and d+ ? usb data pins d ? and d+ are the differential data lines used by the usb module. (see section 11. universal serial bus module (usb) .) the usb module enable bit, usben, in the usb address register (uaddr) controls the pin options for pte4/d ? and pte3/d+. when the usb module is enabled, pte4/d ? and pte3/d+ function as usb data pins d ? and d+. when the usb module is disabled, pte4/d ? and pte3/d+ function as 10ma open-drain high current pins for ps/2 clock and data use. the pullup enable bit, pullen, in the usb control register 3 (ucr3) enables a 1.5k ? ? pin when the usb module is enabled. (see 11.8.8 usb control register 3 .) note: pte4/d ? pin has two programmable pullup resistors. one is used for pte4 when the usb module is disabled and another is used for d ? when the usb module is enabled. t2ch01 and t1ch01 ? timer channel i/o bits the pte2/t2ch01 and pte1/t1ch01 pins are the respective tim2 and tim1 input capture/output compare pins. the edge/level select bits, elsxb and elsxa, determine whether the pte2/t2ch01 and pte1/t1ch01 pins are timer channel i/o pins or general-purpose i/o pins. (see section 10. timer interface module (tim) .) tclk ? timer clock input the pte0/tclk pin is the external clock input for tim1 and tim2. the prescaler select bits, ps[2:0], select pte0/tclk as the tim clock input. when not selected as the tim clock, pte0/tclk is available for general purpose i/o. (see section 10. timer interface module (tim) .) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port e MC68HC908JB16 ? rev. 1.0 technical data motorola input/output (i/o) ports 277 note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the tim. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. 14.6.2 data direction register e data direction register e determines whether each port e pin is an input or an output. writing a logic 1 to a ddre bit enables the output buffer for the corresponding port e pin; a logic 0 disables the output buffer. ddre[4:0] ? data direction register e bits these read/write bits control port e data direction. reset clears ddre[4:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note: avoid glitches on port e pins by writing to the port e data register before changing data direction register e bits from 0 to 1. figure 14-13 shows the port e i/o circuit logic. address: $0009 bit 7654321bit 0 read: 0 0 0 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 00000000 = unimplemented figure 14-12. data direction register e (ddre) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908JB16 ? rev. 1.0 278 input/output (i/o) ports motorola figure 14-13. port e i/o circuit when bit ddrex is a logic 1, reading address $0008 reads the ptex data latch. when bit ddrex is a logic 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 14-3 summarizes the operation of the port e pins. 14.7 port options all pins of port a, port c, and port e have programmable pullup resistors. port d has programmable led drive capability; ptd5 ? ptd2 each have 10ma high current sink, and ptd1 ? ptd0 each have 25ma high current sink. table 14-5. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0 x (1) notes : 1. x = don ? t care. input, hi-z (2) 2. hi-z = high impedance. ddre[4:0] pin pte[4:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddre[4:0] pte[4:0] pte[4:0] read ddre ($0009) write ddre ($0009) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port options MC68HC908JB16 ? rev. 1.0 technical data motorola input/output (i/o) ports 279 14.7.1 port option control register the port option control register controls the pullup options for port a, port c, and port e pins. it also controls the drive configuration on port d. pte20p ? pins pte[2:0] pullup enable this read/write bit controls the pullup option for the pte2 ? pte0 pins, regardless whether the pins are input or output. 1 = configure pte2 ? pte0 to have internal pullups 0 = disconnect pte2 ? pte0 internal pullups ptdldd ? led direct drive control this read/write bit controls the output current capability of ptd5 ? ptd2 pins. when set, each port pin has 10ma current sink limit. an led can be connected directly between the port pin and v dd without the need of a series resistor. 1 = ptd5 ? ptd2 configured for direct led drive capability; when a pin is set as an output, the pin is an open-drain pin with 10ma current sink limit 0 = ptd5 ? ptd2 configured as standard open-drain i/o port pins ptdildd ? infrared led drive control this read/write bit controls the output current capability of ptd1 and ptd0 pins. when set, each port pin has 25ma current sink capability. an infrared led can be connected directly between the port pin and v dd . address: $001d bit 7654321bit 0 read: pte20p ptdldd ptdildd pte4p pte3p pcp r pap write: reset:00000000 r=reserved figure 14-14. port option control register (pocr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908JB16 ? rev. 1.0 280 input/output (i/o) ports motorola 1 = ptd1 and ptd0 configured for infrared led drive capability; when a pin is set as an output, the pin is an open-drain pin with 25ma current sink capability 0 = ptd1 and ptd0 configured as standard open-drain i/o port pins pte4p ? pin pte4 pullup enable this read/write bit controls the pullup option for the pte4 pin when the pin is configured as an input and the usb module is disabled. 1 = configure pte4 to have internal pullup 0 = disconnect pte4 internal pullup note: when the usb module is enabled, the pullup controlled by pte4p is disconnected; pte4/d ? pin functions as d ? which has a 1.5k ? 11.8.8 usb control register 3 .) pte3p ? pin pte3 pullup enable this read/write bit controls the pullup option for the pte3 pin when the pin is configured as an input and the usb module is disabled. 1 = configure pte3 to have internal pullup 0 = disconnect pte3 internal pullup pcp ? port c pullup enable this read/write bit controls the pullup option for the ptc1 and ptc0 pins. when set, a pullup device is connected when a pin is configured as an input. 1 = configure port c to have internal pullups 0 = disconnect port c internal pullups pap ? port a pullup enable this read/write bit controls the pullup option for the pta7 ? pta0 pins. when set, a pullup device is connected when a pin is configured as an input. 1 = configure port a to have internal pullups 0 = disconnect port a internal pullups f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola external interrupt (irq) 281 technical data ? MC68HC908JB16 section 15. external interrupt (irq) 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 15.5 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 15.6 pte4/d ? pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 15.7 irq module during break interrupts . . . . . . . . . . . . . . . . . . .285 15.8 irq status and control register . . . . . . . . . . . . . . . . . . . . . . 286 15.9 irq option control register. . . . . . . . . . . . . . . . . . . . . . . . . . 287 15.2 introduction the irq module provides two external interrupt inputs: one dedicated irq pin and one shared port pin, pte4/d ? . 15.3 features features of the irq module include: two external interrupt pins, irq and pte4/d ? irq interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge low leakage irq pin for external rc wake up input selectable internal pullup resistor f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) technical data MC68HC908JB16 ? rev. 1.0 282 external interrupt (irq) motorola 15.4 functional description a logic 0 applied to the external interrupt pin can latch a cpu interrupt request. figure 15-1 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until one of the following actions occurs: vector fetch ? a vector fetch automatically generates an interrupt acknowledge signal that clears the irq latch. software clear ? software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (iscr). writing a logic 1 to the ack bit clears the irq latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is falling-edge-triggered and is software- configurable to be either falling-edge or low-level-triggered. the mode bit in the iscr controls the triggering sensitivity of the irq pin. when the interrupt pin is edge-triggered only, the cpu interrupt request remains set until a vector fetch, software clear, or reset occurs. when the interrupt pin is both falling-edge and low-level-triggered, the cpu interrupt request remains set until both of the following occur: vector fetch or software clear return of the interrupt pin to logic one the vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. as long as the pin is low, the interrupt request remains pending. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. when set, the imask bit in the iscr mask all external interrupt requests. a latched interrupt request is not presented to the interrupt priority logic unless the imask bit is clear. note: the interrupt mask (i) in the condition code register (ccr) masks all interrupt requests, including external interrupt requests. (see 8.6 exception control .) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola external interrupt (irq) 283 figure 15-1. irq module block diagram addr. register name bit 7654321bit 0 $001c irq option control register (iocr) read: 0 0 0 0 0 pte4if pte4ie irqpd write: reset:00000000 $001e irq status and control register (iscr) read: 0 0 0 0 irqf 0 imask mode write: ack reset:00000000 = unimplemented figure 15-2. irq i/o register summary ack imask dq ck clr irq high interrupt to mode select logic irq ff request "1" mode voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd i nternal pullup device dq ck clr "1" pte4if pte4ie pte4 irq irqpd read iocr to pte4 pullup enable circuitry f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) technical data MC68HC908JB16 ? rev. 1.0 284 external interrupt (irq) motorola 15.5 irq pin the irq pin has a low leakage for input voltages ranging from 0v to v dd ; suitable for applications using rc discharge circuitry to wake up the mcu. a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. if the mode bit is set, the irq pin is both falling-edge-sensitive and low- level-sensitive. with mode set, both of the following actions must occur to clear irq: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a logic 1 to the ack bit in the interrupt status and control register (iscr). the ack bit is useful in applications that poll the irq pin and require software to clear the irq latch. writing to the ack bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ack does not affect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack bit latches another interrupt request. if the irq mask bit, imask, is clear, the cpu loads the program counter with the vector address at locations $fff8 and $fff9. return of the irq pin to logic one ? as long as the irq pin is at logic zero, irq remains active. the vector fetch or software clear and the return of the irq pin to logic one may occur in any order. the interrupt request remains pending as long as the irq pin is at logic zero. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge-sensitive only. with mode clear, a vector fetch or software clear immediately clears the irq latch. the irqf bit in the iscr register can be used to check for pending interrupts. the irqf bit is not affected by the imask bit, which makes it useful in applications where polling is preferred. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) pte4/d ? pin MC68HC908JB16 ? rev. 1.0 technical data motorola external interrupt (irq) 285 use the bih or bil instruction to read the logic level on the irq pin. note: when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. an internal pullup resistor to v dd is connected to irq pin; this can be disabled by setting the irqpd bit in the irq option control register ($001c). 15.6 pte4/d ? pin the pte4 pin is configured as an interrupt input to trigger the irq interrupt when the following conditions are satisfied: the usb module is disabled (usben = 0) pte4 pin configured for external interrupt input (pte4ie = 1) setting pte4ie configures the pte4 pin to an input pin with an internal pullup device. the pte4 interrupt is "ored" with the irq input to trigger the irq interrupt (see figure 15-1 . irq module block diagram ). therefore, the irq status and control register affects both the irq pin and the pte4 pin. an interrupt on pte4 also sets the pte4 interrupt flag, pte4if, in the irq option control register (iocr). 15.7 irq module during break interrupts the system integration module (sim) controls whether the irq latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear the latches during the break state. (see section 8. system integration module (sim) .) to allow software to clear the irq latch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latches during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writing to the ack bit in the irq status and control register during the break state has no effect on the irq latch. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) technical data MC68HC908JB16 ? rev. 1.0 286 external interrupt (irq) motorola 15.8 irq status and control register the irq status and control register (iscr) controls and monitors operation of the irq module. the iscr has the following functions: shows the state of the irq flag clears the irq latch masks irq interrupt request controls triggering sensitivity of the irq pin. irqf ? irq flag this read-only status bit is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending ack ? irq interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq latch. ack always reads as logic 0. reset clears ack. imask ? irq interrupt mask bit writing a logic 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. reset clears mode. 1 = irq pin interrupt requests on falling edges and low levels 0 = irq pin interrupt requests on falling edges only address: $001e bit 7654321bit 0 read: 0000irqf0 imask mode write: ack reset: 00000000 = unimplemented figure 15-3. irq status and control register (iscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) irq option control register MC68HC908JB16 ? rev. 1.0 technical data motorola external interrupt (irq) 287 15.9 irq option control register the irq option control register controls and monitors the external interrupt function available on the pte4 pin. it also disables/enables the pullup resistor on the irq pin. controls pullup option on irq pin enables pte4 pin for external interrupts to irq shows the state of the pte4 interrupt flag pte4if ? pte4 interrupt flag this read-only status bit is high when a falling edge on pte4 pin is detected. pte4if bit clears when the iocr is read. 1 = falling edge on pte4 is detected and pte4ie is set 0 = falling edge on pte4 is not detected or pte4ie is clear pte4ie ? pte4 interrupt enable this read/write bit enables or disables the interrupt function on the pte4 pin to trigger the irq interrupt. setting the pte4ie bit and clearing the usben bit in the usb address register configure the pte4 pin for interrupt function to the irq interrupt. setting pte4ie also enables the internal pullup on pte4 pin. 1 = pte4 interrupt enabled; triggers irq interrupt 0 = pte4 interrupt disabled irqpd ? irq pullup disable this read/write bit controls the pullup option for the irq pin. 1 = internal pullup is disconnected 0 = internal pull-up is connected between irq pin and v dd address: $001c bit 7654321bit 0 read: 00000pte4if pte4ie irqpd write: reset: 00000000 = unimplemented figure 15-4. irq option control register (iocr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) technical data MC68HC908JB16 ? rev. 1.0 288 external interrupt (irq) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola keyboard interrupt module (kbi) 289 technical data ? MC68HC908JB16 section 16. keyboard interrupt module (kbi) 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 16.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 16.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 16.6 keyboard initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 16.7 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 16.7.1 keyboard status and control register. . . . . . . . . . . . . . . . 294 16.7.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 295 16.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 16.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 16.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 16.9 keyboard module during break interrupts . . . . . . . . . . . . . . .296 16.2 introduction the keyboard interrupt module (kbi) provides eight independently maskable external interrupts which are accessible via pta0 ? pta7 pins. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data MC68HC908JB16 ? rev. 1.0 290 keyboard interrupt module (kbi) motorola 16.3 features features of the keyboard interrupt module include: eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask hysteresis buffers programmable edge-only or edge- and level-interrupt sensitivity exit from low-power modes 16.4 pin name conventions the kbi share eight i/o pins with eight port a i/o pins. the full name of the i/o pins are listed in table 16-1 . the generic pin name appear in the text that follows. addr.register name bit 7654321bit 0 $0016 keyboard status and control register (kbscr) read: 0 0 0 0 keyf 0 imaskk modek write: ackk reset:00000000 $0017 keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 16-1. i/o register summary table 16-1. pin name conventions full mcu pin name kbi generic pin name pin selected for kbi function by kbiex bit in kbier pta7/kba7 ? pta0/kba0 kba7 ? kba0 kbie7 ? kbie0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola keyboard interrupt module (kbi) 291 16.5 functional description figure 16-2. keyboard module block diagram writing to the kbie7 ? kbie0 bits in the keyboard interrupt enable register independently enables or disables each port a pin as a keyboard interrupt pin. enabling a keyboard interrupt pin also enables its internal pullup device. a logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched when one or more keyboard pins goes low after all were high. the modek bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low.to prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. if the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the modek bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: kbie0 kbie7 . . . dq ck clr v reg modek imaskk keyboard interrupt ff vector fetch decoder ackk internal bus reset kba7 kba0 synchronizer keyf keyboard interrupt request to pullup enable to pullup enable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data MC68HC908JB16 ? rev. 1.0 292 keyboard interrupt module (kbi) motorola vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software may generate the interrupt acknowledge signal by writing a logic 1 to the ackk bit in the keyboard status and control register (kbscr). the ackk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine also can prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the cpu loads the program counter with the vector address at locations $ffe0 and $ffe1. return of all enabled keyboard interrupt pins to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the keyboard interrupt pin is falling-edge- sensitive only. with modek clear, a vector fetch or software clear immediately clears the keyboard interrupt request. reset clears the keyboard interrupt request and the modek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the keyboard status and control register can be used to see if a pending interrupt exists. the keyf bit is not affected by the keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. note: setting a keyboard interrupt enable bit (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a logic 0 for software to read the pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) keyboard initialization MC68HC908JB16 ? rev. 1.0 technical data motorola keyboard interrupt module (kbi) 293 16.6 keyboard initialization when a keyboard interrupt pin is enabled, it takes time for the pullup device to reach a logic 1. therefore, a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. an interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. another way to avoid a false interrupt: 1. configure the keyboard pins as outputs by setting the appropriate ddra bits in data direction register a. 2. write logic 1s to the appropriate port a data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 16.7 i/o registers these registers control and monitor operation of the keyboard module: keyboard status and control register (kbscr) keyboard interrupt enable register (kbier) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data MC68HC908JB16 ? rev. 1.0 294 keyboard interrupt module (kbi) motorola 16.7.1 keyboard status and control register flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard interrupt triggering sensitivity keyf ? keyboard flag bit this read-only bit is set when a keyboard interrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a logic 1 to this write-only bit clears the keyboard interrupt request. ackk always reads as logic 0. reset clears ackk. imaskk ? keyboard interrupt mask bit writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only address: $0016 bit 7654321bit 0 read: 0000keyf0 imaskk modek write: ackk reset:00000000 = unimplemented figure 16-3. keyboard status and control register (kbscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) low-power modes MC68HC908JB16 ? rev. 1.0 technical data motorola keyboard interrupt module (kbi) 295 16.7.2 keyboard interrupt enable register the keyboard interrupt enable register enables or disables each port a pin to operate as a keyboard interrupt pin. kbie7 ? kbie0 ? keyboard interrupt enable bits each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = ptax/kbax pin enabled as keyboard interrupt pin 0 = ptax/kbax not enabled as keyboard interrupt pin 16.8 low-power modes the wait and stop instructions put the mcu in low-power consumption standby modes. 16.8.1 wait mode the keyboard module remains active in wait mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. 16.8.2 stop mode the keyboard module remains active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. address: $0017 bit 7654321bit 0 read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 figure 16-4. keyboard interrupt enable register (kbier) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data MC68HC908JB16 ? rev. 1.0 296 keyboard interrupt module (kbi) motorola 16.9 keyboard module during break interrupts the system integration module (sim) controls whether the keyboard interrupt latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. to allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latch during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writing to the keyboard acknowledge bit (ackk) in the keyboard status and control register during the break state has no effect. (see 16.7.1 keyboard status and control register .) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola computer operating properly (cop) 297 technical data ? MC68HC908JB16 section 17. computer operating properly (cop) 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 17.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 17.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 17.4.1 oscdclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 17.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 17.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 17.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 17.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 17.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 17.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 17.4.8 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . 300 17.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 17.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 17.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 17.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 17.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 17.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 17.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . .302 17.2 introduction the computer operating properly (cop) module contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runaway code. prevent a cop reset by clearing the cop counter periodically. the cop module can be disabled through the copd bit in the config register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) technical data MC68HC908JB16 ? rev. 1.0 298 computer operating properly (cop) motorola 17.3 functional description figure 17-1 shows the structure of the cop module. figure 17-1. cop block diagram the cop counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. if not cleared by software, the cop counter overflows and generates an asynchronous reset after 2 18 ? 2 4 or 2 13 ? 2 4 oscdclk cycles, depending on the state of the cop rate select bit, coprs, in configuration register 1. with a 2 18 ? 2 4 oscdclk cycle overflow option, a 24mhz oscdclk (12mhz crystal) gives a cop timeout period of 10.92ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by clearing the cop counter and stages 12 through 5 of the prescaler. note: service the cop immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. copctl write oscdclk reset vector fetch reset circuit reset status register internal reset sources 12-bit cop prescaler clear all stages 6-bit cop counter cop disable reset copctl write clear copen (from sim) cop counter cop clock cop timeout stop instruction (copd from config) cop rate sel (coprs from config) clear stages 5 ? 12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) i/o signals MC68HC908JB16 ? rev. 1.0 technical data motorola computer operating properly (cop) 299 a cop reset pulls the rst pin low for 32 oscdclk cycles and sets the cop bit in the sim reset status register (srsr). in monitor mode, the cop is disabled if the rst pin or the irq is held at v tst . during the break state, v tst on the rst pin disables the cop. note: place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt subroutine could keep the cop from generating a reset even while the main program is not working properly. 17.4 i/o signals the following paragraphs describe the signals shown in figure 17-1 . 17.4.1 oscdclk oscdclk is the crystal oscillator clock doubler output signal. its frequency is two times the crystal frequency. 17.4.2 stop instruction the stop instruction clears the cop prescaler. 17.4.3 copctl write writing any value to the cop control register (copctl) (see 17.5 cop control register ) clears the cop counter and clears bits 12 through 5 of the prescaler. reading the cop control register returns the low byte of the reset vector. 17.4.4 power-on reset the power-on reset (por) circuit clears the cop prescaler 4096 oscdclk cycles after power-up. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) technical data MC68HC908JB16 ? rev. 1.0 300 computer operating properly (cop) motorola 17.4.5 internal reset an internal reset clears the cop prescaler and the cop counter. 17.4.6 reset vector fetch a reset vector fetch occurs when the vector address appears on the data bus. a reset vector fetch clears the cop prescaler. 17.4.7 copd (cop disable) the copd signal reflects the state of the cop disable bit (copd) in the config register. (see figure 17-2 .) 17.4.8 coprs (cop rate select) the coprs signal reflects the state of the cop rate select bit (coprs) in the config register. (see figure 17-2 .) coprs ? cop rate select bit coprs selects the cop timeout period. reset clears coprs. 1 = cop timeout period is 2 13 ? 2 4 oscdclk cycles 0 = cop timeout period is 2 18 ? 2 4 oscdclk cycles copd ? cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled address: $001f bit 7654321bit 0 read: lvidr lvi5or3 urstd lvid ssrec coprs stop copd write: reset:0*0*0*0*0000 * lvidr, lvi5or3, urstd, and lvid, are reset by por or lvi reset only. figure 17-2. configuration register (config) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) cop control register MC68HC908JB16 ? rev. 1.0 technical data motorola computer operating properly (cop) 301 17.5 cop control register the cop control register is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 17.6 interrupts the cop does not generate cpu interrupt requests. 17.7 monitor mode when monitor mode is entered with v tst on the irq pin, the cop is disabled as long as v tst remains on the irq pin or the rst pin. when monitor mode is entered by having blank reset vectors and not having v tst on the irq pin, the cop is automatically disabled until a por occurs. 17.8 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clears cop counter (any value) reset: unaffected by reset figure 17-3. cop control register (copctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) technical data MC68HC908JB16 ? rev. 1.0 302 computer operating properly (cop) motorola 17.8.1 wait mode the cop remains active during wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter in a cpu interrupt routine. 17.8.2 stop mode stop mode turns off the oscdclk input to the cop and clears the cop prescaler. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. to prevent inadvertently turning off the cop with a stop instruction, a configuration option is available that disables the stop instruction. when the stop bit in the configuration register has the stop instruction is disabled, execution of a stop instruction results in an illegal opcode reset. 17.9 cop module during break mode the cop is disabled during a break interrupt when v tst is present on the rst pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola low-voltage inhibit (lvi) 303 technical data ? MC68HC908JB16 section 18. low-voltage inhibit (lvi) 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 18.4.1 low v dd detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 18.4.2 low v reg detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 18.5 lvi control and configuration . . . . . . . . . . . . . . . . . . . . . . . . 305 18.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 18.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 18.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 18.2 introduction this section describes the low-voltage inhibit (lvi) module, which monitors the voltage on the v dd pin and v reg pin. and can force a reset when the v dd or v reg voltage falls below the lvi trip falling voltage. 18.3 features features of the lvi module include: independent voltage monitoring circuits for v dd and v reg independent lvi circuit disable for v dd and v reg selectable lvi trip voltage for v dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) technical data MC68HC908JB16 ? rev. 1.0 304 low-voltage inhibit (lvi) motorola figure 18-1. lvi module block diagram 18.4 functional description figure 18-1 shows the structure of the lvi module. the lvi is enabled out of reset. the lvi module contains independent bandgap reference circuit and comparator for monitoring the v dd voltage and the v reg voltage. an lvi reset performs a mcu internal reset and drives the rst pin low to provide low-voltage protection to external peripheral devices. 18.4.1 low v dd detector the low v dd detector circuit monitors the v dd voltage and forces a lvi reset when the v dd voltage falls below the trip voltage. the lvi5or3 bit in the configuration register (config) selects the trip point voltage. the v dd lvi circuit can be disabled by the setting the lvid bit in config. see 8.4.2.5 low-voltage inhibit (lvi) reset for details of the interaction between the sim and the lvi. low v dd lvid detector v dd lvi reset v dd > v lvr = 0 v dd < v lvr = 1 low v reg lvidr detector v reg v dd > v lvrr = 0 v dd < v lvrr = 1 lvi5or3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) lvi control and configuration MC68HC908JB16 ? rev. 1.0 technical data motorola low-voltage inhibit (lvi) 305 18.4.2 low v reg detector the low v reg detector circuit monitors the v reg voltage and forces a lvi reset when the v reg voltage falls below the trip voltage. the v reg lvi circuit can be disabled by the setting the lvidr bit in config. note: there is no lvi circuit for v rega . 18.5 lvi control and configuration three bits in the configuration register (config) control the operation of the lvi module. lvidr ? lvi disable bit for v reg lvidr disables the lvi circuit for v reg . 1 = lvi circuit for v reg disabled 0 = lvi circuit for v reg enabled lvi5or3 ? lvi trip point voltage select bit for v dd lvi5or3 selects the trip point voltage of the lvi circuit for v dd . see section 20. electrical specifications for the trip voltage tolerances. 1 = lvi trips at 3.3v 0 = lvi trips at 2.4v lvid ? lvi disable bit for v dd lvid disables the lvi circuit for v dd . 1 = lvi circuit for v dd disabled 0 = lvi circuit for v dd enabled address: $001f bit 7654321bit 0 read: lvidr lvi5or3 urstd lvid ssrec coprs stop copd write: reset: 0* 0* 0* 0* 0 0 0 0 = unimplemented * lvidr, lvi5or3, urstd, and lvid bits are reset by por (power-on reset) or lvi reset only. figure 18-2. configuration register (config) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) technical data MC68HC908JB16 ? rev. 1.0 306 low-voltage inhibit (lvi) motorola 18.6 low-power modes the stop and wait instructions put the mcu in low power- consumption standby modes. 18.6.1 wait mode if enabled, the lvi module remains active in wait mode. 18.6.2 stop mode if enabled, the lvi module remains active in stop mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola break module (brk) 307 technical data ? MC68HC908JB16 section 19. break module (brk) 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 19.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 19.4.1 flag protection during break interrupts . . . . . . . . . . . . . . .310 19.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 310 19.4.3 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . 310 19.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 310 19.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310 19.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 19.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 19.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 19.6.1 break status and control register. . . . . . . . . . . . . . . . . . .311 19.6.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . .312 19.6.3 sim break status register . . . . . . . . . . . . . . . . . . . . . . . . . 312 19.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . .314 19.2 introduction this section describes the break module. the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) technical data MC68HC908JB16 ? rev. 1.0 308 break module (brk) motorola 19.3 features features of the break module include: accessible input/output (i/o) registers during the break interrupt cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts 19.4 functional description when the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the cpu. the cpu then loads the instruction register with a software interrupt instruction (swi) after completion of the current cpu instruction. the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu-generated address (the address in the program counter) matches the contents of the break address registers. software writes a logic 1 to the brka bit in the break status and control register. when a cpu-generated address matches the contents of the break address registers, the break interrupt begins after the cpu completes its current instruction. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 19-1 shows the structure of the break module. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) functional description MC68HC908JB16 ? rev. 1.0 technical data motorola break module (brk) 309 figure 19-1. break module block diagram iab15 ? iab8 iab7 ? iab0 8-bit comparator 8-bit comparator control break address register low break address register high iab15 ? iab0 break addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 0 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe0c break address register high (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 note: writing a logic 0 clears sbsw. = unimplemented r = reserved figure 19-2. break module i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) technical data MC68HC908JB16 ? rev. 1.0 310 break module (brk) motorola 19.4.1 flag protection during break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. 19.4.2 cpu during break interrupts the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. 19.4.3 tim during break interrupts a break interrupt stops the timer counters. 19.4.4 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. 19.5 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 19.5.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the return address on the stack if sbsw is set (see section 8. system integration module (sim) ). clear the sbsw bit by writing logic 0 to it. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) break module registers MC68HC908JB16 ? rev. 1.0 technical data motorola break module (brk) 311 19.5.2 stop mode a break interrupt causes exit from stop mode and sets the sbsw bit in the break status register. 19.6 break module registers these registers control and monitor operation of the break module: break status and control register (brkscr) break address register high (brkh) break address register low (brkl) sim break status register (sbsr) sim break flag control register (sbfcr) 19.6.1 break status and control register the break status and control register (brkscr) contains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break address register matches. clear brke by writing a logic 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled on 16-bit address match address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 19-3. break status and control register (brkscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) technical data MC68HC908JB16 ? rev. 1.0 312 break module (brk) motorola brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a logic 1 to brka generates a break interrupt. clear brka by writing a logic 0 to it before exiting the break routine. reset clears the brka bit. 1 = (when read) break address match 0 = (when read) no break address match 19.6.2 break address registers the break address registers (brkh and brkl) contain the high and low bytes of the desired breakpoint address. reset clears the break address registers. 19.6.3 sim break status register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit from wait mode. the flag is useful in applications requiring a return to wait mode after exiting from a break interrupt. address: $fe0c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 19-4. break address register high (brkh) address: $fe0d bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 19-5. break address register low (brkl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) break module registers MC68HC908JB16 ? rev. 1.0 technical data motorola break module (brk) 313 sbsw ? sim break stop/wait bit this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. reset clears sbsw. 1 = stop mode or wait mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break interrupt routine. the user can modify the return address on the stack by subtracting one from it. the following code is an example. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note reset: 0 note: writing a logic 0 clears sbsw. r=reserved figure 19-6. sim break status register (sbsr) ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) technical data MC68HC908JB16 ? rev. 1.0 314 break module (brk) motorola 19.6.4 sim break flag control register the sim break flag control register (sbfcr) contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r=reserved figure 19-7. sim break flag control register (sbfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola electrical specifications 315 technical data ? MC68HC908JB16 section 20. electrical specifications 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 20.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . .316 20.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 317 20.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 20.6 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 318 20.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 20.8 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 20.9 timer interface module characteristics . . . . . . . . . . . . . . . . . 320 20.10 usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 320 20.11 usb low-speed source electrical characteristics . . . . . . . . 321 20.12 usb signaling levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 20.13 cgm electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 322 20.14 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 324 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data MC68HC908JB16 ? rev. 1.0 316 electrical specifications motorola 20.2 introduction this section contains electrical and timing specifications. 20.3 absolute maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. note: this device is not guaranteed to operate properly at the maximum ratings. refer to 20.6 dc electrical characteristics for guaranteed operating conditions. note: this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss ? 0.3 to +6.0 v input voltage pte4/d ? , pte3/d+ others v in v ss ? 1.0 to v dd +0.3 v ss ? 0.3 to v dd +0.3 v mode entry voltage, irq pin v tst v ss ? 0.3 to +8 v maximum current per pin excluding v dd and v ss i ? 55 to +150 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications functional operating range MC68HC908JB16 ? rev. 1.0 technical data motorola electrical specifications 317 20.4 functional operating range 20.5 thermal characteristics characteristic symbol value unit operating temperature range t a 0 to 70 ja 95 70 c/w i/o pin power dissipation p i/o user-determined w power dissipation (1) notes : 1. power dissipation is a function of temperature. p d p d = (i dd c) w constant (2) 2. k is a constant unique to the device. k can be determined for a known t a and measure p d . with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c ) + p d 2 ja w/ c average junction temperature t j t a + (p d ja ) c maximum junction temperature t jm 100 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data MC68HC908JB16 ? rev. 1.0 318 electrical specifications motorola 20.6 dc electrical characteristics characteristic (1) symbol min typ (2) max unit regulator output voltage v reg v rega0 3.0 2.9 3.3 3.3 3.6 3.7 v output high voltage (i load = ? 2.0 ma) pta0 ? pta7, ptc0 ? ptc1, pte0 ? pte2 v oh v dd ? 0.8 ?? v output low voltage (i load = 1.6 ma) all i/o pins (i load = 25 ma) ptd0 ? ptd1 in ildd mode (i load = 10 ma) pte3 ? pte4 with usb is disabled v ol ? ? ? ? ? ? 0.4 0.5 0.4 v input high voltage osc1 all ports, irq , rst v ih 0.7 ? ? v reg v dd v input low voltage osc1 all ports, irq , rst v il v ss v ss ? ? 0.3 ? ptd5 in ldd mode i ol 10 13 20 ma v dd supply current, v dd = 5.25v, f op = 6mhz run, with low speed usb (3) run, with usb suspended (3) wait, with low speed usb (4) wait, with usb suspended (4) stop (0 ? ? ? ? ? 7.0 6.5 3.0 2.5 60 8.5 8.0 5.0 4.0 100 ma ma ma ma ?? ?? ? ? ? ? 12 8 pf por re-arm voltage (6) v por 0 ? 100 mv por rise-time ramp rate (7) r por 0.035 ?? v/ms monitor mode entry voltage v tst v dd + 2.5 8 v pullup resistors port a, port c, pte0 ? pte2, rst , irq (to v dd ) pte3 ? pte4 with usb module disabled (to v dd ) d ? with usb module enabled (to v reg ) r pu 20 4 1.1 35 5 1.5 50 6 2.0 k ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications control timing MC68HC908JB16 ? rev. 1.0 technical data motorola electrical specifications 319 20.7 control timing 20.8 oscillator characteristics notes : 1. v dd = 4.0 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measurements at midpoint of voltage range, 25 ? ? pins; all ports configured as inputs; osc2 capacitance linearly affects wait i dd 5. stop i dd measured with usb in suspend mode; osc1 grounded; no port pins sourcing current. 6. maximum is highest voltage that por is guaranteed. 7. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. characteristic (1) notes : 1. v dd = 4.0 to 5.5 vdc; v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit internal operating frequency (2) 2. some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. f op ? 6mhz rst input pulse width low (3) 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 125 ? ns characteristic symbol min typ max unit crystal frequency (1) notes : 1. the usb module is designed to operate with f xclk = 12 mhz. f xclk 112 12 mhz external clock reference frequency (1), (2) 2. no more than 10% duty cycle deviation from 50%. f xclk dc 12 12 mhz crystal load capacitance (3) 3. consult crystal vendor data sheet. c l ?? ? crystal fixed capacitance (3) c 1 ? 2 ? crystal tuning capacitance (3) c 2 ? 2 ? feedback bias resistor r b ? 10 m ? ? series resistor (3), (4) 4. not required for high-frequency crystals. r s ?? ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data MC68HC908JB16 ? rev. 1.0 320 electrical specifications motorola 20.9 timer interface module characteristics 20.10 usb dc electrical characteristics characteristic symbol min max unit input capture pulse width t tih, t til 1/f op ? ns input clock pulse width t tch, t tcl (1/f op ) + 5 ? ns characteristic (1) notes : 1. v dd = 4.0 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol conditions min typ max unit hi-z state data line leakage i lo 0 v electrical specifications technical data MC68HC908JB16 ? rev. 1.0 322 electrical specifications motorola 20.12 usb signaling levels 20.13 cgm electrical characteristics bus state signaling levels transmit receive differential 1 d+ > v oh (min) and d ? < v ol (max) (d+) ? (d ? ) > 200 mv differential 0 d ? > v oh (min) and d ? < v ol (max) (d ? ) ? (d+) > 200 mv single-ended 0 (se0) d+ and d ? < v ol (max) d+ and d ? < v il (max) data j state (low speed) differential 0 differential 0 data k state (low speed) differential 1 differential 1 idle state (low speed) na d ? > v ihz (min) and d+ < v il (max) resume state differential 1 differential 1 start of packet (sop) data lines switch from idle to k state end of packet (eop) se0 for approximately 2 bit times (1) followed by a j state for 1 bit time notes : 1. the width of eop is defined in bit times relative to the speed of transmission. se0 for ? < v il (max) for ? ? 6 3 10 5 ma ma cgm regulator output voltage v rega0 2.9 3.3 3.7 v cgm output high voltage (i load = ? 2.0 ma) v oh v rega0 ? 0.8 ?? v cgm output low voltage (i load = 1.6 ma) v ol ?? 0.4 v cgm output equivalent capacitance c out ?? 12 pf cgm output rise and fall time r l = 2k ? ?? 8ns output resistive load r l 2 ?? k ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications cgm electrical characteristics MC68HC908JB16 ? rev. 1.0 technical data motorola electrical specifications 323 output capacitive load c l ?? 10 pf pll frequency list rx lo 1 rx lo 2 rx lo 3 rx lo 4 rx lo 5 ? 26.54 26.59 26.64 26.69 26.74 ? mhz pll output signal frequency accuracy exclude crystal osc tolerance ? ? hz ppm pll output signal phase noise level at ?? 40 ? dbc/hz vco frequency range 26 ? 28 mhz pll lock duration channel to channel (3) ? 10 ? ms wait/stop mode to active (4) ? 20 ? ms duration for lock bit detection within ? 10 ? ms pll stop duration pll module from active to disable mode. ?? 1ms pll output sideband noise level (6) at offset >4khz at offset >42.5khz ? ? 40 ? 50 ? dbc pll output channel intermodulation products (7) at offset >42.5khz ?? 50 ? dbc notes : 1. v dda = 4.0 to 5.5 vdc, v ssa = 0 vdc, t a = t l to t h , with the pre-defined programming setting for the pll (see 13.10 pre-defined vco output frequency settings ) and under steady state condition, unless otherwise noted. 2. typical values reflect average measurements at midpoint of voltage range, 25 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data MC68HC908JB16 ? rev. 1.0 324 electrical specifications motorola 20.14 flash memory characteristics characteristic symbol min max unit ram data retention voltage v rdr 1.3 ? v flash block size ? 512 bytes flash programming size ? 64 bytes flash read bus clock frequency f read (1) notes : 1. f read is defined as the frequency range for which the flash memory can be read. 32 k 8.4 m hz flash block erase time t erase (2) 2. if the page erase time is longer than t erase (min), there is no erase-disturb, but it reduced the endurance of the flash memory. 10 ? ms flash mass erase time t merase (3) 3. if the mass erase time is longer than t merase (min), there is no erase-disturb, but it reduces the endurance of the flash memory. 200 ? ms flash pgm/erase to hven set up time t nvs 5 ? s flash high-voltage hold time t nvh 5 ? s flash high-voltage hold time (mass erase) t nvhl 100 ? s flash program hold time t pgs 10 ? s flash program time t prog 20 40 s flash return to read time t rcv (4) 4. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clearing hven to logic 0. 1 ? s flash cumulative program hv period t hv (5) 5. t hv is defined as the cumulative high voltage programming time to the same row before next erase. ? 8ms flash row erase endurance (6) 6. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ? 10k ? cycles flash row program endurance (7) 7. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ? 10k ? cycles flash data retention time (8) 8. the flash is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. ? 10 ? years f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola mechanical specifications 325 technical data ? MC68HC908JB16 section 21. mechanical specifications 21.1 contents 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 21.3 32-pin low-profile quad flat pack (lqfp) . . . . . . . . . . . . . . 326 21.4 28-pin small outline integrated circuit (soic) . . . . . . . . . . . 327 21.2 introduction this section gives the dimensions for: 32-pin low-profile quad flat pack (case #873a) 28-pin small outline integrated circuit package (case #751f) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications technical data MC68HC908JB16 ? rev. 1.0 326 mechanical specifications motorola 21.3 32-pin low-profile quad flat pack (lqfp) figure 21-1. 32-pin lqfp (case #873a) detail y a s1 v b 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae ? ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ? ab ? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ? t ? , ? u ? , and ? z ? to be determined at datum plane ? ab ? . 5. dimensions s and v to be determined at seating plane ? ac ? . 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ? ab ? . 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc detail ad a1 b1 v1 4x s 4x b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref 9 ? t ? ? z ? ? u ? t ? u 0.20 (0.008) z ac t ? u 0.20 (0.008) z ab 0.10 (0.004) ac ? ac ? ? ab ? m 8x ? t ? , ? u ? , ? z ? t ? u m 0.20 (0.008) z ac f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications 28-pin small outline integrated circuit (soic) MC68HC908JB16 ? rev. 1.0 technical data motorola mechanical specifications 327 21.4 28-pin small outline integrated circuit (soic) figure 21-2. 28-pin soic (case #751f) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. j k f 1 15 14 28 -a- -b- 28x 14x d p s a m 0.010 (0.25) b s t m 0.010 (0.25) b m 26x g -t- seating plane c x 45 r m dim min max min max inches millimeters a 17.80 18.05 0.701 0.711 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m p 10.01 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications technical data MC68HC908JB16 ? rev. 1.0 328 mechanical specifications motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908JB16 ? rev. 1.0 technical data motorola ordering information 329 technical data ? MC68HC908JB16 section 22. ordering information 22.1 contents 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 22.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 22.2 introduction this section contains ordering numbers for the MC68HC908JB16. 22.3 mc order numbers table 22-1. mc order numbers mc order number package operating temperature range MC68HC908JB16dw 28-pin soic 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information technical data MC68HC908JB16 ? rev. 1.0 330 ordering information motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu minato-ku, tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: h t t p : / / m o t orola . c o m / semi c onduc t o rs information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ? typical ? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ? typicals ? must be validated for each customer application by customer ? s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. all other product or service n a m e s a r e t he pr o pe r ty o f t h e i r res p ec t i v e o w ne r s. m o t o ro l a , i n c. i s a n e q ual opportunity/affirmative action employer. ? motorola, inc. 2002 5/2002 rev. 1.0 MC68HC908JB16/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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